yosys/tests/arch/ice40/latches.ys

read_verilog ../common/latches.v
design -save read

hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4

select -assert-none t:SB_LUT4 %% t:* %D


design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4

select -assert-none t:SB_LUT4 %% t:* %D


design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4

select -assert-none t:SB_LUT4 %% t:* %D