yosys/techlibs/greenpak4/cells_sim.v

mirror of https://github.com/YosysHQ/yosys.git
`timescale 1ns/1ps

`include "cells_sim_ams.v"
`include "cells_sim_digital.v"
`include "cells_sim_wip.v"
Fixed extra semicolon 2016-05-08 06:14:18 +02:00			`timescale 1ns/1ps
Added simulation timescale declaration 2016-05-08 06:13:47 +02:00
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-06 01:33:24 +02:00			`include "cells_sim_ams.v"
			`include "cells_sim_digital.v"
Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-08-29 22:23:23 +02:00			`include "cells_sim_wip.v"