mirror of https://github.com/YosysHQ/yosys.git
16 lines
326 B
Plaintext
16 lines
326 B
Plaintext
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read_verilog -sv <<EOT
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module smoke_initstate (
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input resetn,
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input clk,
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input a
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);
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always @(posedge clk) begin
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assert property ($stable(a));
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assert property ($changed(a));
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assert property ($rose(a));
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assert property ($fell(a));
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assume(resetn == !$initstate);
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end
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endmodule
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EOT
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