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yosys/backends/firrtl/test.sh

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tests: use /usr/bin/env for bash.
2023-08-12 03:59:39 +02:00
#!/usr/bin/env bash
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
set -ex
More progress on Firrtl backend. Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
2016-11-22 02:28:17 +01:00
cd ../../
make
cd backends/firrtl
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
More progress on Firrtl backend. Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
2016-11-22 02:28:17 +01:00
../../yosys -q -p 'prep -nordff; write_firrtl test.fir' $1
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
More progress on Firrtl backend. Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
2016-11-22 02:28:17 +01:00
firrtl -i test.fir -o test_out.v -ll Info
../../yosys -p "
read_verilog $1
rename Top gold
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
read_verilog test_out.v
More progress on Firrtl backend. Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
2016-11-22 02:28:17 +01:00
rename Top gate
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
prep
More progress in FIRRTL back-end
2016-11-18 02:41:29 +01:00
memory_map
Progress in FIRRTL back-end
2016-11-18 00:32:35 +01:00
miter -equiv -flatten gold gate miter
hierarchy -top miter
sat -verify -prove trigger 0 -set-init-zero -seq 10 miter
More progress on Firrtl backend. Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
2016-11-22 02:28:17 +01:00
"