yosys/tests/verilog/unbased_unsized.ys

read_verilog -sv unbased_unsized.sv
hierarchy
proc
flatten
opt -full
async2sync
select -module top
sat -verify -tempinduct -prove-asserts -show-all
sv: fix some edge cases for unbased unsized literals - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst` 2021-03-03 20:36:19 +01:00			`read_verilog -sv unbased_unsized.sv`
			`hierarchy`
			`proc`
			`flatten`
			`opt -full`
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. 2024-01-22 17:44:05 +01:00			`async2sync`
sv: fix some edge cases for unbased unsized literals - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst` 2021-03-03 20:36:19 +01:00			`select -module top`
tests: remove -seq 1 from sat with -tempinduct where possible * When used with -tempinduct mode, -seq <N> causes assertions to be ignored in the first N steps. While this has uses for reset modelling, for these test cases it is unnecessary and could lead to failures slipping through uncaught 2024-10-03 16:34:19 +02:00			`sat -verify -tempinduct -prove-asserts -show-all`