mirror of https://github.com/YosysHQ/yosys.git
50 lines
1.4 KiB
Verilog
50 lines
1.4 KiB
Verilog
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module FF (input C, D, output Q);
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parameter INIT = 1'b0;
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if (INIT === 1'b1) begin
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FFPE _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(1'b0), .CE(1'b1), .Q(Q));
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end else begin
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FFCE _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(1'b0), .CE(1'b1), .Q(Q));
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end
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endmodule
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module FF_N (input C, D, output Q);
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parameter INIT = 1'b0;
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if (INIT === 1'b1) begin
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FFPE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(1'b0), .CE(1'b1), .Q(Q));
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end else begin
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FFCE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(1'b0), .CE(1'b1), .Q(Q));
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end
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endmodule
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module FFC (input C, D, CLR, output Q);
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FFCE _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(CLR), .CE(1'b1), .Q(Q));
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endmodule
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module FFC_N (input C, D, CLR, output Q);
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FFCE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .CLR(CLR), .CE(1'b1), .Q(Q));
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endmodule
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module FFP (input C, D, PRE, output Q);
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FFPE _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(PRE), .CE(1'b1), .Q(Q));
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endmodule
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module FFP_N (input C, D, CLR, output Q);
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FFPE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .PRE(PRE), .CE(1'b1), .Q(Q));
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endmodule
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module FFR (input C, D, R, output Q);
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FFRE _TECHMAP_REPLACE_ (.C(C), .D(D), .R(R), .CE(1'b1), .Q(Q));
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endmodule
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module FFR_N (input C, D, R, output Q);
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FFRE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .R(R), .CE(1'b1), .Q(Q));
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endmodule
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module FFS (input C, D, S, output Q);
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FFSE _TECHMAP_REPLACE_ (.C(C), .D(D), .S(S), .CE(1'b1), .Q(Q));
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endmodule
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module FFS_N (input C, D, S, output Q);
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FFSE_N _TECHMAP_REPLACE_ (.C(C), .D(D), .S(S), .CE(1'b1), .Q(Q));
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endmodule
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