docs/source/code_examples/techmap/red_or3x1_test.ys

read_verilog red_or3x1_test.v
hierarchy -check -top test

techmap -map red_or3x1_map.v;;

splitnets -ports
show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v
Progress in presentation 2014-02-16 13:45:47 +01:00			`read_verilog red_or3x1_test.v`
			`hierarchy -check -top test`

			`techmap -map red_or3x1_map.v;;`

			`splitnets -ports`
docs: moving code examples 2023-11-14 12:55:39 +13:00			`show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v`