Files

4 lines
67 B
Verilog
Raw Permalink Normal View History

2014-06-22 12:50:29 +02:00
module test(input a, output x, y);
2023-12-13 11:34:42 +13:00
assign x = a, y = a;
2014-06-22 12:50:29 +02:00
endmodule