This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-08-22 14:17:27 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
emil/proc_rom-src-test
yosys
/
tests
/
asicworld
/
README
T
Add File
New File
Upload File
Apply Patch
Copy Permalink
2 lines
59 B
Plaintext
Raw
Permalink
Normal View
History
Unescape
Escape
Another block of spelling fixes
2015-08-14 13:23:01 -07:00
Borrowed Verilog examples from http://www.asic-world.com/.
Reference in New Issue
Copy Permalink