Files
yosys/tests/opt/opt_share_mux_tree.v

19 lines
302 B
Verilog
Raw Permalink Normal View History

module opt_share_test(
2019-08-03 12:35:46 +02:00
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [1:0] sel,
output reg [15:0] res
);
2019-07-26 11:36:48 +02:00
2019-08-03 12:35:46 +02:00
always @* begin
case(sel)
0: res = a + b;
1: res = a - b;
2: res = a + c;
default: res = 16'bx;
endcase
end
2019-07-26 11:36:48 +02:00
endmodule