mirror of https://github.com/YosysHQ/yosys.git
13 lines
215 B
Plaintext
13 lines
215 B
Plaintext
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read_verilog <<EOF
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module top(input [3:0] a, input [3:0] b, output [7:0] y);
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assign y = a * b;
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endmodule
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module top2(input [7:0] a, input [7:0] b, output [15:0] y);
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assign y = a * b;
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endmodule
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EOF
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synth
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timeest
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