fix-xaiger2-empty-cell-input-broken-test/tests/verilog/asgn_expr.ys

read_verilog -sv asgn_expr.sv
proc
async2sync
sat -verify -prove-asserts -show-all
sv: support assignments within expressions 2023-09-05 22:19:28 -04:00			`read_verilog -sv asgn_expr.sv`
			`proc`
tests: Run async2sync before sat and/or sim to handle $check cells 2024-01-22 17:44:05 +01:00			`async2sync`
sv: support assignments within expressions 2023-09-05 22:19:28 -04:00			`sat -verify -prove-asserts -show-all`