mirror of https://github.com/YosysHQ/yosys.git
6 lines
120 B
Verilog
6 lines
120 B
Verilog
|
|
`default_nettype none
|
||
|
|
module latch_1990_gate
|
||
|
|
(output wire [1:0] x);
|
||
|
|
assign x = 2'b10;
|
||
|
|
endmodule // latch_1990_gate
|