yosys/tests/techmap/dlatchlibmap_proc_formal.ys

##################################################################

read_verilog -sv -icells <<EOT

module top(input E, D, S, R, output [3:0] Q);

	always_latch
		if      (R)  Q[0] <= 1'b0;
		else if (S)  Q[0] <= 1'b1;
		else if (E)  Q[0] <= D;

	always_latch
		if      (S)  Q[1] <= 1'b1;
		else if (R)  Q[1] <= 1'b0;
		else if (E)  Q[1] <= D;

assign Q[3:2] = ~Q[1:0];

endmodule

EOT

proc
opt
read_liberty dlatchlibmap_dlatchsr_s.lib

copy top top_unmapped
dfflibmap -liberty dlatchlibmap_dlatchsr_s.lib top

clk2fflogic
flatten
opt_clean -purge
miter -equiv -make_assert -flatten top_unmapped top miter

# Prove that this is equivalent
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter

##################################################################

delete top miter

copy top_unmapped top
dfflibmap -liberty dlatchlibmap_dlatchsr_r.lib top

clk2fflogic
flatten
miter -equiv -make_assert -flatten top_unmapped top miter

# Prove that this is equivalent
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter

##################################################################

delete top miter

copy top_unmapped top
dfflibmap -liberty dlatchlibmap_dlatchsr_mixedpol.lib top

clk2fflogic
flatten
miter -equiv -make_assert -flatten top_unmapped top miter

# Prove that this is equivalent
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter

##################################################################

delete top miter

copy top_unmapped top
dfflibmap -liberty dlatchlibmap_dlatchsr_not_data.lib top

clk2fflogic
flatten
miter -equiv -make_assert -flatten top_unmapped top miter

# Prove that this is equivalent
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter