yosys/tests/sim/simple_assign.vcd

$version Yosys $end
$scope module simple_assign $end
$var wire 1 n2 in $end
$var wire 1 n1 out $end
$upscope $end
$enddefinitions $end
#0
#5
b1 n1
b1 n2
#10
b0 n1
b0 n2
Assume x values for missing signal data in FST Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com> 2024-10-02 11:18:19 +02:00			`$version Yosys $end`
			`$scope module simple_assign $end`
			`$var wire 1 n2 in $end`
			`$var wire 1 n1 out $end`
			`$upscope $end`
			`$enddefinitions $end`
			`#0`
			`#5`
			`b1 n1`
			`b1 n2`
			`#10`
			`b0 n1`
End of file fix 2026-06-23 07:23:41 +02:00			`b0 n2`