yosys/docs/source/yosys_internals/flow/index.rst

Internal flow
=============

A (usually short) synthesis script controls Yosys.

These scripts contain three types of commands:

- **Frontends**, that read input files (usually Verilog);
- **Passes**, that perform transformations on the design in memory;
- **Backends**, that write the design in memory to a file (various formats are
  available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).

.. toctree::
	:maxdepth: 3

	overview
	control_and_data
	verilog_frontend
Reorganising documentation Also changing to furo theme. 2023-08-02 23:20:29 +02:00			`Internal flow`
			`=============`

Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert. 2023-08-02 23:20:29 +02:00			`A (usually short) synthesis script controls Yosys.`

Correcting plurals 2023-12-04 23:22:00 +01:00			`These scripts contain three types of commands:`
Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert. 2023-08-02 23:20:29 +02:00
			`- Frontends, that read input files (usually Verilog);`
			`- Passes, that perform transformations on the design in memory;`
			`- Backends, that write the design in memory to a file (various formats are`
			`available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).`

Remove trailing whitespaces 2026-06-23 07:24:59 +02:00			`.. toctree::`
Some tidy up 2023-08-14 02:13:29 +02:00			`:maxdepth: 3`
Reorganising documentation Also changing to furo theme. 2023-08-02 23:20:29 +02:00
			`overview`
			`control_and_data`
			`verilog_frontend`