dffsr-sr-correct-dfflibmap/tests/verilog/doubleslash.ys

read_verilog -sv <<EOT
module doubleslash
  (input  logic   a,
   input  logic   b,
   output logic   z);

  logic \a//b ;

  assign \a//b = a & b;
  assign z = ~\a//b ;

endmodule : doubleslash
EOT

hierarchy
proc
opt -full

write_verilog doubleslash.v
design -reset
read_verilog doubleslash.v
preprocessor: do not destroy double slash escaped identifiers 2021-08-25 21:34:26 +02:00			`read_verilog -sv <<EOT`
			`module doubleslash`
			`(input logic a,`
			`input logic b,`
			`output logic z);`

			`logic \a//b ;`

			`assign \a//b = a & b;`
			`assign z = ~\a//b ;`

			`endmodule : doubleslash`
			`EOT`

			`hierarchy`
			`proc`
			`opt -full`

			`write_verilog doubleslash.v`
fixup verilog doubleslash test 2021-12-30 00:06:23 -07:00			`design -reset`
			`read_verilog doubleslash.v`