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emil/codeowners-verilog-ast
yosys
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aiger
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halfadder.aag
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2019-02-04 16:46:24 -08:00
aag 7 2 0 2 3
2
4
6
12
6 13 15
12 2 4
14 3 5
i0 x
i1 y
o0 s
o1 c
c
half adder
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