codeowners-verilog-ast/techlibs/ice40/tests/test_arith.ys

read_verilog test_arith.v
synth_ice40
rename test gate

read_verilog test_arith.v
rename test gold

miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter

synth_ice40 -top gate

read_verilog test_arith.v
rename test gold

miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
Added ice40 test_arith 2015-04-18 09:33:34 +02:00			`read_verilog test_arith.v`
			`synth_ice40`
			`rename test gate`

			`read_verilog test_arith.v`
			`rename test gold`

			`miter -equiv -flatten -make_outputs gold gate miter`
			`sat -verify -prove trigger 0 -show-ports miter`
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 2019-08-12 12:06:45 -07:00
			`synth_ice40 -top gate`

			`read_verilog test_arith.v`
			`rename test gold`

			`miter -equiv -flatten -make_outputs gold gate miter`
			`sat -verify -prove trigger 0 -show-ports miter`