mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-06 11:59:46 +02:00
23 lines
271 B
Verilog
23 lines
271 B
Verilog
|
|
||
|
|
module NOT(A, Y);
|
||
|
|
input A;
|
||
|
|
output Y = ~A;
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module NAND(A, B, Y);
|
||
|
|
input A, B;
|
||
|
|
output Y = ~(A & B);
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module NOR(A, B, Y);
|
||
|
|
input A, B;
|
||
|
|
output Y = ~(A | B);
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module DFF(C, D, Q);
|
||
|
|
input C, D;
|
||
|
|
output reg Q;
|
||
|
|
always @(posedge C)
|
||
|
|
Q <= D;
|
||
|
|
endmodule
|