2019-11-19 10:19:00 +00:00
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OBJS += techlibs/intel_alm/synth_intel_alm.o
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# Techmap
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2020-05-23 12:52:13 +01:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_unmap.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/abc9_model.v))
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2019-11-19 10:19:00 +00:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_sim.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
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2020-04-25 17:25:59 +01:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_sim.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
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2020-04-16 12:24:04 +01:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
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2021-05-15 14:23:22 +01:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/misc_sim.v))
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2019-11-19 10:19:00 +00:00
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2020-07-27 14:21:05 +01:00
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$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
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2019-11-19 10:19:00 +00:00
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# RAM
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2020-07-26 19:28:10 +01:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
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2022-03-09 16:40:32 +00:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
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2019-11-19 10:19:00 +00:00
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
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# Miscellaneous
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
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