51 lines
1.7 KiB
XML
51 lines
1.7 KiB
XML
v {xschem version=3.1.0 file_version=1.2
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}
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G {
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y <= not a after 0.1 ns ;}
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K {type=subcircuit
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function0="1 ~"
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @VCCPIN @VSSPIN @symname wn=@wn lln=@lln wp=@wp lp=@lp m=@m"
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template="name=x1 m=1
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+ wn=10u lln=1.2u wp=10u lp=1.2u
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+ VCCPIN=VCC VSSPIN=VSS"
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extra="VCCPIN VSSPIN"
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generic_type="m=integer wn=real lln=real wp=real lp=real VCCPIN=string VSSPIN=string"
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verilog_stop=true}
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V {assign #150 y=~a ;}
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S {}
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E {}
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P 4 5 350 -380 350 -140 480 -140 480 -380 350 -380 {dash=4}
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T {@name x @m} 353.75 -395 0 0 0.2 0.2 {}
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T {@symname} 486.25 -395 0 1 0.2 0.2 {}
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N 420 -280 420 -240 {lab=y}
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N 420 -260 480 -260 {lab=y}
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N 380 -310 380 -210 {lab=a}
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N 350 -260 380 -260 {lab=a}
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N 420 -310 470 -310 {lab=VCCPIN}
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N 470 -340 470 -310 {lab=VCCPIN}
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N 420 -340 470 -340 {lab=VCCPIN}
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N 420 -210 470 -210 {lab=VSSPIN}
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N 470 -210 470 -180 {lab=VSSPIN}
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N 420 -180 470 -180 {lab=VSSPIN}
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N 420 -360 420 -340 {lab=VCCPIN}
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N 420 -180 420 -160 {lab=VSSPIN}
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C {opin.sym} 480 -260 0 0 {name=p1 lab=y verilog_type=wire}
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C {ipin.sym} 350 -260 0 0 {name=p2 lab=a}
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C {use.sym} 300 -540 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- use ieee.std_logic_arith.all;
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-- use ieee.std_logic_unsigned.all;
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-- library SYNOPSYS;
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-- use SYNOPSYS.ATTRIBUTES.ALL;
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}
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C {p.sym} 400 -310 0 0 {name=m2 model=cmosp w=wp l=lp m=1 }
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C {lab_pin.sym} 420 -360 0 0 {name=p149 lab=VCCPIN}
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C {lab_pin.sym} 420 -160 0 0 {name=p3 lab=VSSPIN}
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C {n.sym} 400 -210 0 0 {name=m1 model=cmosn w=wn l=lln m=1}
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C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"}
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C {verilog_timescale.sym} 660 -217.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
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