31 lines
1.1 KiB
Plaintext
31 lines
1.1 KiB
Plaintext
v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=label
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format="*.alias @lab"
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template="name=l1 sig_type=std_logic lab=xxx"}
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V {}
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S {}
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E {}
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B 5 -0.3125 39.6875 0.3125 40.3125 {name=p dir=in}
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P 1 7 0 40 -40 0 -520 0 -560 40 -520 80 -40 80 0 40 {fill=full}
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