49 lines
1.8 KiB
XML
49 lines
1.8 KiB
XML
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 510 -350 510 -170 {lab=Z}
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N 450 -350 450 -170 {lab=A}
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N 480 -130 480 -110 {lab=E}
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N 420 -110 480 -110 {lab=E}
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N 420 -290 450 -290 {lab=A}
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N 480 -410 480 -390 {lab=EN}
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N 420 -410 480 -410 {lab=EN}
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N 510 -290 540 -290 {lab=Z}
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N 480 -350 480 -320 {lab=VCCPIN}
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N 480 -210 480 -170 {lab=VSSPIN}
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C {p.sym} 480 -370 3 1 {name=m60 model=cmosp w=WP l=2.4u m=1
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}
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C {n.sym} 480 -150 3 0 {name=m1 model=cmosn w=WN l=2.4u m=1}
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C {iopin.sym} 540 -290 0 0 {name=p1 lab=Z}
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C {iopin.sym} 420 -290 0 1 {name=p2 lab=A}
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C {ipin.sym} 420 -410 0 0 {name=p3 lab=EN}
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C {ipin.sym} 420 -110 0 0 {name=p4 lab=E}
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C {lab_pin.sym} 480 -320 3 0 {name=l1 sig_type=std_logic lab=VCCPIN}
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C {lab_pin.sym} 480 -210 3 1 {name=l2 sig_type=std_logic lab=VSSPIN}
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C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"}
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C {noconn.sym} 480 -210 2 0 {name=l4}
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C {noconn.sym} 480 -320 2 0 {name=l5}
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