69 lines
2.5 KiB
XML
69 lines
2.5 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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V {assign #200 y = ~(a & b);
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}
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S {}
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E {}
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N 370 -280 410 -280 {lab=y}
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N 240 -510 300 -510 {lab=VCCPIN}
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N 240 -480 300 -480 {lab=VCCPIN}
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N 240 -450 240 -280 {lab=y}
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N 370 -140 390 -140 {lab=VSSPIN}
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N 180 -480 200 -480 {lab=a}
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N 290 -140 330 -140 {lab=b}
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N 290 -360 310 -360 {lab=b}
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N 300 -510 300 -480 {lab=VCCPIN}
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N 370 -190 370 -170 {lab=#net1}
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N 370 -220 390 -220 {lab=VSSPIN}
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N 370 -280 370 -250 {lab=y}
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N 350 -390 410 -390 {lab=VCCPIN}
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N 350 -360 410 -360 {lab=VCCPIN}
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N 410 -390 410 -360 {lab=VCCPIN}
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N 350 -330 350 -280 {lab=y}
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N 240 -280 350 -280 {lab=y}
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N 350 -280 370 -280 {lab=y}
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N 180 -220 330 -220 {lab=a}
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N 180 -480 180 -220 {lab=a}
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N 290 -360 290 -140 {lab=b}
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N 110 -480 180 -480 {lab=a}
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N 110 -360 290 -360 {lab=b}
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N 350 -510 350 -390 {lab=VCCPIN}
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N 240 -510 350 -510 {lab=VCCPIN}
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N 150 -510 240 -510 {lab=VCCPIN}
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N 280 -110 370 -110 {lab=VSSPIN}
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C {opin.sym} 410 -280 0 0 {name=p1 lab=y verilog_type=wire}
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C {ipin.sym} 110 -480 0 0 {name=p2 lab=a}
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C {p.sym} 220 -480 0 0 {name=m2 model=cmosp w=wpa l=lpa m=1
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}
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C {p.sym} 330 -360 0 0 {name=m1 model=cmosp w=wpb l=lpb m=1
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}
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C {ipin.sym} 110 -360 0 0 {name=p3 lab=b}
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C {lab_pin.sym} 150 -510 0 0 {name=l1 sig_type=std_logic lab=VCCPIN}
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C {lab_pin.sym} 280 -110 0 0 {name=l2 sig_type=std_logic lab=VSSPIN}
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C {lab_pin.sym} 390 -220 0 1 {name=l3 sig_type=std_logic lab=VSSPIN}
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C {lab_pin.sym} 390 -140 0 1 {name=l4 sig_type=std_logic lab=VSSPIN}
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C {n.sym} 350 -220 0 0 {name=m3 model=cmosn w=wna l=lna m=1}
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C {n.sym} 350 -140 0 0 {name=m4 model=cmosn w=wnb l=lnb m=1}
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C {title.sym} 170 0 0 0 {name=l5 author="Stefan Schippers"}
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C {verilog_timescale.sym} 660 -257.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
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