62 lines
1.9 KiB
Plaintext
62 lines
1.9 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=opamp
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format="@spiceprefix@name @#0 @#1 @VCC @VNN @#2 @model"
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tedax_format="footprint @name @footprint
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value @name @value
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device @name @device
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spicedev @name @spicedev
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spiceval @name @spiceval
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comptag @name @comptag"
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template="name=U1:1
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model=LM358 device=LM358
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footprint=so(8)
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numslots=2
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VCC=VCC
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VNN=VNN"
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extra="VCC VNN"
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extra_pinnumber="8 4"}
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V {}
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S {}
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E {}
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L 4 110 0 130 0 {}
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L 4 -80 -40 -60 -40 {}
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L 4 -80 40 -60 40 {}
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L 4 -60 -70 110 0 {}
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L 4 -60 70 110 0 {}
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L 4 -60 -70 -60 70 {}
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B 5 -82.5 -42.5 -77.5 -37.5 {name=PLUS sig_type=std_logic dir=in pinnumber=3:5}
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B 5 -82.5 37.5 -77.5 42.5 {name=MINUS sig_type=std_logic dir=in pinnumber=2:6}
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B 5 127.5 -2.5 132.5 2.5 {name=OUT sig_type=std_logic dir=out pinnumber=1:7}
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T {@device} -48.5 -11 0 0 0.3 0.3 {}
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T {@name} 0 -62 0 0 0.3 0.3 {}
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T {@#2:pinnumber} 115 -14 0 0 0.2 0.2 {layer=13}
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T {@#0:pinnumber} -65 -54 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -65 26 0 1 0.2 0.2 {layer=13}
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T {OUT} 90 -4 0 1 0.2 0.2 {}
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T {PLUS} -55 -44 0 0 0.2 0.2 {}
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T {MINUS} -55 36 0 0 0.2 0.2 {}
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