53 lines
1.7 KiB
Plaintext
53 lines
1.7 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=regulator
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format="@spiceprefix@name @pinlist @symname"
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verilog_format="assign @#2 = @#0 ;"
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tedax_format="footprint @name @footprint
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value @name @value
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device @name @device
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spicedev @name @spicedev
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spiceval @name @spiceval
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comptag @name @comptag"
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template="name=U1 device=7805 footprint=TO220"}
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V {}
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S {}
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E {}
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L 4 -60 0 -50 0 {}
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L 4 50 0 60 0 {}
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L 4 -50 -20 50 -20 {}
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L 4 50 -20 50 20 {}
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L 4 -50 20 50 20 {}
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L 4 -50 -20 -50 20 {}
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L 4 0 20 0 30 {}
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B 5 -62.5 -2.5 -57.5 2.5 {name=IN dir=in pinnumber=1}
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B 5 -2.5 27.5 2.5 32.5 {name=GND dir=inout pinnumber=2}
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B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out pinnumber=3}
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T {@name} -10 -17.5 0 0 0.2 0.2 {}
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T {@device} -17.5 -32.5 0 0 0.2 0.2 {}
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T {@#0:pinnumber} -47.5 -5 0 0 0.2 0.2 {}
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T {@#1:pinnumber} -5 7.5 0 0 0.2 0.2 {}
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T {@#2:pinnumber} 47.5 -5 0 1 0.2 0.2 {}
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