57 lines
2.2 KiB
XML
57 lines
2.2 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 480 -400 480 -360 { lab=#net1}
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N 480 -400 550 -400 { lab=#net1}
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N 480 -300 480 -250 { lab=0}
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N 610 -400 680 -400 { lab=Y1}
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N 330 -400 370 -400 { lab=A1}
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N 330 -460 370 -460 { lab=B1}
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C {ipin.sym} 80 -170 0 0 {name=p1 lab=A}
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C {opin.sym} 330 -170 0 0 {name=p4 lab=Y}
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C {bsource.sym} 480 -330 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((min(V(A1),V(B1))-VCC/2)*100))'"
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}
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C {lab_pin.sym} 330 -400 0 0 {name=l2 sig_type=std_logic lab=A1}
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C {lab_pin.sym} 480 -250 0 0 {name=l3 sig_type=std_logic lab=0}
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C {res.sym} 580 -400 1 0 {name=R1
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value='ROUT'
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 680 -400 0 1 {name=l5 sig_type=std_logic lab=Y1}
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C {ammeter.sym} 110 -170 3 0 {name=Va}
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C {lab_pin.sym} 140 -170 0 1 {name=l6 sig_type=std_logic lab=A1}
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C {ammeter.sym} 300 -170 3 0 {name=Vy}
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C {lab_pin.sym} 270 -170 0 0 {name=l7 sig_type=std_logic lab=Y1}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {ipin.sym} 80 -110 0 0 {name=p2 lab=B}
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C {ammeter.sym} 110 -110 3 0 {name=Va1}
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C {lab_pin.sym} 140 -110 0 1 {name=l4 sig_type=std_logic lab=B1}
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C {lab_pin.sym} 330 -460 0 0 {name=l8 sig_type=std_logic lab=B1}
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C {parax_cap.sym} 370 -390 0 0 {name=C1 gnd=0 value=8f m=1}
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C {parax_cap.sym} 370 -450 0 0 {name=C2 gnd=0 value=8f m=1}
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C {parax_cap.sym} 630 -390 0 0 {name=C3 gnd=0 value=8f m=1}
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