200 lines
5.1 KiB
XML
200 lines
5.1 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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B 2 970 -610 1960 -220 {flags=graph
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y1=-93
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y2=1.3
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=-1.00075
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x2=7.45087
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divx=10
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subdivx=8
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node="\\"out db20()\\""
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color=4
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dataset=-1
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unitx=1
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logx=1
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logy=0
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}
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N 100 -550 100 -520 {lab=IN}
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N 650 -510 670 -510 {lab=OUT}
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N 270 -550 430 -550 {lab=PLUS}
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N 190 -550 210 -550 {lab=#net1}
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N 200 -600 200 -550 {lab=#net1}
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N 200 -660 650 -660 {lab=OUT}
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N 650 -660 650 -510 {lab=OUT}
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N 630 -510 650 -510 {lab=OUT}
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N 650 -510 650 -360 {lab=OUT}
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N 410 -360 650 -360 {lab=OUT}
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N 410 -470 410 -360 {lab=OUT}
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N 410 -470 430 -470 {lab=OUT}
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N 850 -540 850 -520 {lab=0}
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N 800 -530 850 -530 {lab=0}
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N 100 -550 130 -550 {lab=IN}
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C {code_shown.sym} 20 -320 0 0 {name=CONTROL vhdl_ignore=true place=end value=".control
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listing e
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save all
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run
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write hpf.raw
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let response = db(v(out)/v(in))
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settype decibel response
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plot xlog response
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gnuplot hpf response xlog
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.endc
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"}
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C {code_shown.sym} 390 -310 0 0 {name=DIRECTIVES vhdl_ignore=true place=end value=".ac oct 100 0.1 100meg
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.param pi = 3.1415926
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.param Q = 1
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.param freq = 20
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.param w0 = 2.0*pi*freq
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.param k = 4*Q**2
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.param R = 10k
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.param C = 1/(sqrt(k)*R*w0)
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"}
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C {title.sym} 160 -30 0 0 {name=l7 author="Stefan Schippers"}
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C {vsource.sym} 100 -490 0 0 {name=v2 value="ac 1"}
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C {gnd.sym} 100 -460 0 0 {name=l14 lab=0}
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C {capa.sym} 240 -550 1 1 {name=C1 m=1 value=C footprint=1206 device="ceramic capacitor"}
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C {lab_wire.sym} 400 -550 0 0 {name=l8 sig_type=std_logic lab=PLUS}
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C {res.sym} 340 -520 0 0 {name=R6 value='k*R' footprint=1206 device=resistor m=1}
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C {gnd.sym} 340 -490 0 0 {name=l2 lab=0}
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C {vsource.sym} 850 -570 0 0 {name=v6 value=12}
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C {vsource.sym} 850 -490 0 0 {name=v1 value=12}
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C {lm741.sym} 530 -510 0 0 {name=X1 model=LM741 device=LM741 footprint="SO(8)"
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}
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C {code.sym} 760 -290 0 0 {name=MODELS vhdl_ignore=true value="*//////////////////////////////////////////////////////////
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*LM741 OPERATIONAL AMPLIFIER MACRO-MODEL
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*//////////////////////////////////////////////////////////
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*
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* connections: non-inverting input
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* | inverting input
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* | | positive power supply
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* | | | negative power supply
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* | | | | output
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* | | | | |
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* | | | | |
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.SUBCKT LM741 1 2 99 50 28
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*
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*Features:
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*Improved performance over industry standards
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*Plug-in replacement for LM709,LM201,MC1439,748
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*Input and output overload protection
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*
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****************INPUT STAGE**************
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*
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IOS 2 1 20N
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*^Input offset current
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R1 1 3 250K
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R2 3 2 250K
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I1 4 50 100U
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R3 5 99 517
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R4 6 99 517
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Q1 5 2 4 QX
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Q2 6 7 4 QX
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*Fp2=2.55 MHz
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C4 5 6 60.3614P
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*
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***********COMMON MODE EFFECT***********
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*
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I2 99 50 1.6MA
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*^Quiescent supply current
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EOS 7 1 POLY(1) 16 49 1E-3 1
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*Input offset voltage.^
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R8 99 49 40K
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R9 49 50 40K
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*
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*********OUTPUT VOLTAGE LIMITING********
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V2 99 8 1.63
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D1 9 8 DX
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D2 10 9 DX
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V3 10 50 1.63
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*
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**************SECOND STAGE**************
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*
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EH 99 98 99 49 1
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G1 98 9 5 6 2.1E-3
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*Fp1=5 Hz
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R5 98 9 95.493MEG
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C3 98 9 333.33P
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*
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***************POLE STAGE***************
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*
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*Fp=30 MHz
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G3 98 15 9 49 1E-6
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R12 98 15 1MEG
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C5 98 15 5.3052E-15
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*
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*********COMMON-MODE ZERO STAGE*********
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*
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*Fpcm=300 Hz
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G4 98 16 3 49 3.1623E-8
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L2 98 17 530.5M
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R13 17 16 1K
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*
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**************OUTPUT STAGE**************
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*
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F6 50 99 POLY(1) V6 450U 1
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E1 99 23 99 15 1
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R16 24 23 25
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D5 26 24 DX
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V6 26 22 0.65V
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R17 23 25 25
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D6 25 27 DX
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V7 22 27 0.65V
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V5 22 21 0.18V
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D4 21 15 DX
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V4 20 22 0.18V
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D3 15 20 DX
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L3 22 28 100P
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RL3 22 28 100K
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*
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***************MODELS USED**************
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*
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.MODEL DX D(IS=1E-15)
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.MODEL QX NPN(BF=625)
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*
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.ENDS
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"}
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C {lab_pin.sym} 100 -550 0 0 {name=l23 sig_type=std_logic lab=IN}
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C {res.sym} 200 -630 0 0 {name=R7 value=R footprint=1206 device=resistor m=1}
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C {capa.sym} 160 -550 1 1 {name=C2 m=1 value=C footprint=1206 device="ceramic capacitor"}
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C {gnd.sym} 530 -450 0 0 {name=l1 lab=VEE}
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C {vdd.sym} 530 -570 0 0 {name=l5 lab=VCC}
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C {gnd.sym} 850 -460 0 0 {name=l3 lab=VEE}
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C {vdd.sym} 850 -600 0 0 {name=l4 lab=VCC}
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C {gnd.sym} 800 -530 0 0 {name=l6 lab=0}
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C {opin.sym} 670 -510 0 0 {name=p9 lab=OUT}
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C {launcher.sym} 1115 -175 0 0 {name=h5
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descr="load ngspice waves"
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tclcommand="
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xschem raw_read $netlist_dir/hpf.raw ac
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"
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}
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