40 lines
1.5 KiB
XML
40 lines
1.5 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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C {ipin.sym} 110 -220 0 0 {name=p1 lab=A}
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C {ipin.sym} 110 -190 0 0 {name=p2 lab=B}
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C {opin.sym} 210 -220 0 0 {name=p4 lab=S}
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C {opin.sym} 210 -190 0 0 {name=p5 lab=COUT}
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C {title.sym} 160 -30 0 0 {name=l2}
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C {lab_pin.sym} 470 -270 0 0 {name=l6 lab=A}
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C {lab_pin.sym} 470 -230 0 0 {name=l7 lab=B}
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C {lab_pin.sym} 570 -160 0 1 {name=p7 lab=COUT}
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C {lab_pin.sym} 470 -180 0 0 {name=p3 lab=A}
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C {lab_pin.sym} 470 -140 0 0 {name=p6 lab=B}
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C {lab_pin.sym} 570 -250 0 1 {name=l3 lab=S}
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C {xor_ngspice.sym} 510 -250 0 0 {name=x1 ROUT=1000}
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C {and_ngspice.sym} 510 -160 0 0 {name=x2 ROUT=1000}
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