46 lines
1.8 KiB
XML
46 lines
1.8 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 420 -320 640 -320 { lab=S[5:0]}
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N 760 -320 810 -320 { lab=COUNT[5:0]}
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N 800 -350 800 -320 { lab=COUNT[5:0]}
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N 280 -350 800 -350 { lab=COUNT[5:0]}
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N 280 -350 280 -320 { lab=COUNT[5:0]}
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N 420 -300 460 -300 { lab=COUT[5:0]}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {lab_wire.sym} 520 -320 0 1 {name=l42 lab=S[5:0]}
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C {lab_pin.sym} 460 -300 0 1 {name=p43 lab=COUT[5:0]}
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C {flip_flop_ngspice.sym} 700 -300 0 0 {name=x2[5:0]}
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C {lab_pin.sym} 810 -320 0 1 {name=p11 lab=COUNT[5:0]}
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C {lab_pin.sym} 640 -300 0 0 {name=p13 lab=CK}
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C {lab_pin.sym} 640 -280 0 0 {name=p14 lab=RST}
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C {half_adder_ngspice.sym} 350 -310 0 0 {name=x1[5:0]}
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C {lab_pin.sym} 280 -300 0 0 {name=p5 lab=COUT[4:0],D}
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C {ipin.sym} 120 -120 0 0 { name=p1 lab=RST }
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C {ipin.sym} 120 -140 0 0 { name=p2 lab=D}
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C {opin.sym} 220 -160 0 0 { name=p4 lab=COUNT[5:0] }
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C {ipin.sym} 120 -160 0 0 { name=p6 lab=CK }
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