47 lines
1.6 KiB
Plaintext
47 lines
1.6 KiB
Plaintext
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1"
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}
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V {}
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S {}
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E {}
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L 4 -40 -50 -40 50 {}
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L 4 40 0 60 0 {}
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L 4 -60 30 -40 30 {}
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L 4 -40 -50 40 0 {}
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L 4 -40 50 40 0 {}
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L 4 -60 -30 -40 -30 {}
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B 5 -62.5 -32.5 -57.5 -27.5 {name=PLUS dir=in }
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B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out }
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B 5 -62.5 27.5 -57.5 32.5 {name=MINUS dir=in }
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T {@symname} -32 44 0 0 0.3 0.3 {}
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T {@name} -10 -48.25 0 0 0.2 0.2 {}
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T {PLUS} -38.75 -30.25 0 0 0.2 0.2 {}
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T {OUT} 28.75 -5.25 0 1 0.2 0.2 {}
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T {MINUS} -38.75 18.5 0 0 0.2 0.2 {}
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T {@#PLUS:spice_get_voltage} -38.125 -17.34375 0 0 0.0625 0.0625 {layer=15}
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T {@#MINUS:spice_get_voltage} -38.125 13.90625 0 0 0.0625 0.0625 {layer=15}
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T {@#OUT:spice_get_voltage} 25.625 -8.59375 0 1 0.0625 0.0625 {layer=15}
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