45 lines
1.5 KiB
Plaintext
45 lines
1.5 KiB
Plaintext
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname RUP=@RUP RDOWN=@RDOWN"
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template="name=x1 RUP=2000 RDOWN=1000"
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}
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V {}
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S {}
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E {}
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L 4 20 0 40 0 {}
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L 4 -40 0 -20 0 {}
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L 4 -20 -20 20 0 {}
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L 4 -20 -20 -20 20 {}
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L 4 -20 20 20 0 {}
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B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out }
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B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in }
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T {@symname} -47.5 34 0 0 0.3 0.3 {}
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T {@name} 25 -22 0 0 0.2 0.2 {}
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T {Y} 7.5 -6.5 0 1 0.2 0.2 {}
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T {A} -17.5 -6.5 0 0 0.2 0.2 {}
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T {RUP=@RUP
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RDOWN=@RDOWN} -25 -52 0 0 0.2 0.2 {}
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T {@#1:net_name} -22.5 6.25 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 17.5 6.25 0 0 0.15 0.15 {layer=15}
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