94 lines
3.4 KiB
XML
94 lines
3.4 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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T {Buck Regulator
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This circuit is a simplified buck regulator.
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Instead of a digital logic block controlling the regulator,
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a simple triangle wave and comparator generates the switch pulses. } 20 -790 0 0 0.6 0.6 {}
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T {Copyright (C) 2011 DJ Delorie (dj delorie com)
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Distributed under the terms of the GNU General Public License,
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either verion 2 or (at your choice) any later version.} 20 -150 0 0 0.4 0.4 {}
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N 60 -470 180 -470 {lab=nin}
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N 60 -470 60 -340 {lab=nin}
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N 210 -230 210 -220 {lab=0}
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N 60 -220 210 -220 {lab=0}
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N 60 -280 60 -220 {lab=0}
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N 210 -430 210 -350 {lab=ntriangle}
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N 360 -340 360 -220 {lab=0}
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N 210 -220 360 -220 {lab=0}
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N 360 -470 360 -400 {lab=ndiode}
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N 240 -470 360 -470 {lab=ndiode}
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N 360 -470 400 -470 {lab=ndiode}
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N 360 -220 570 -220 {lab=0}
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N 570 -280 570 -220 {lab=0}
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N 520 -470 570 -470 {lab=nout}
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N 570 -470 570 -400 {lab=nout}
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N 690 -470 690 -400 {lab=nout}
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N 570 -470 690 -470 {lab=nout}
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N 690 -280 690 -220 {lab=0}
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N 570 -220 690 -220 {lab=0}
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N 230 -430 570 -430 {lab=nout}
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C {vsource.sym} 60 -310 0 0 {name=Vin value="DC pwl 0 0 50u 5V"}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {gnd.sym} 60 -220 0 0 {name=l2 lab=0}
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C {switch_ngspice.sym} 210 -470 3 0 {name=S1 model=swmod}
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C {diode.sym} 360 -370 2 0 {name=D1 model=DIODE area=1}
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C {vsource.sym} 210 -320 0 0 {name=Vpulse value="pulse -0.06 0.14 0
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+ 3.32u 3.32u 1f 6.67u"}
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C {vsource.sym} 210 -260 0 0 {name=Vset value=3.3}
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C {ammeter.sym} 490 -470 3 0 {name=Vmeas}
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C {capa.sym} 570 -310 0 0 {name=C1
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m=1
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value=47u
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footprint=1206
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device="ceramic capacitor"}
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C {ammeter.sym} 570 -370 0 0 {name=Vcap}
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C {ammeter.sym} 690 -370 0 0 {name=Vload}
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C {res.sym} 690 -310 0 0 {name=Rload
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value=13.2
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footprint=1206
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device=resistor
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m=1}
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C {ind.sym} 430 -470 3 1 {name=L1
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m=1
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value=18u
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footprint=1206
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device=inductor}
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C {code.sym} 780 -470 0 0 {name=MODELS value=".MODEL DIODE D(IS=1.139e-08 RS=0.99 CJO=9.3e-12 VJ=1.6 M=0.411 BV=30 EG=0.7 )
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.MODEL swmod SW(VT=0 VH=0.01 RON=1 ROFF=100000)
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"}
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C {code_shown.sym} 790 -320 0 0 {name=COMMANDS value=".save all
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.tran 0.001us 0.25ms
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"}
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C {lab_wire.sym} 650 -470 0 0 {name=l3 sig_type=std_logic lab=nout}
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C {lab_wire.sym} 350 -470 0 0 {name=l4 sig_type=std_logic lab=ndiode}
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C {lab_wire.sym} 140 -470 0 0 {name=l5 sig_type=std_logic lab=nin}
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C {lab_wire.sym} 210 -360 0 0 {name=l6 sig_type=std_logic lab=ntriangle}
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C {launcher.sym} 90 -580 0 0 {name=h1
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descr="Ctrl-click to go to Delorie's
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project page for info"
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url="http://www.delorie.com/electronics/spice-stuff"}
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