610 lines
20 KiB
XML
610 lines
20 KiB
XML
v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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L 3 250 -270 250 -120 {}
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L 3 410 -270 410 -170 {}
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L 3 570 -270 570 -120 {}
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L 4 150 -100 250 -100 {}
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L 4 250 -120 250 -100 {}
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L 4 250 -120 570 -120 {}
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L 4 570 -120 570 -100 {}
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L 4 570 -100 690 -100 {}
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L 4 150 -170 410 -170 {}
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L 4 410 -170 410 -150 {}
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L 4 410 -150 570 -150 {}
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L 4 570 -170 570 -150 {}
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L 4 570 -170 690 -170 {}
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L 7 1090 -260 2520 -260 {}
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B 2 270 -1020 680 -860 {flags=graph,unlocked
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y1 = 0
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y2 = 0.9
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divy = 5
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x1=1.9099218e-07
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x2=3.4920522e-07
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divx=5
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subdivx=4
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unitx=n
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node="cal%0
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saout"
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color="8 6"
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linewidth_mult=1.0
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hilight_wave=-1
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dataset=188
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rawfile=$netlist_dir/autozero_comp.raw
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sim_type=tran
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rainbow=0
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hcursor1_y=0.13350312
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hcursor2_y=0.58853305}
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B 2 270 -1160 680 -1030 {flags=graph,unlocked
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y1 = 0.647319
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y2 = 0.652563
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x1=1.9099218e-07
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x2=3.4920522e-07
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unitx=n
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divx=5
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subdivx=2
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node="plus%0
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minus%0"
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color="4 5"
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dataset=-1
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linewidth_mult=1.0
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divy=3
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subdivy=1
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rawfile=$netlist_dir/autozero_comp.raw
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sim_type=tran}
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B 2 270 -1320 680 -1160 {flags=graph,unlocked
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y1 = 0.647319
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y2 = 0.652563
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x1=1.9099218e-07
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x2=3.4920522e-07
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unitx=n
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divx=5
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subdivx=2
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node="plus%0
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minus%0"
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color="4 5"
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dataset=-1
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linewidth_mult=1.0
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divy=3
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subdivy=1
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rawfile=$netlist_dir/autozero_comp.raw
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sim_type=tran}
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B 2 270 -1450 680 -1330 {flags=graph,unlocked
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y1 = 0.647319
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y2 = 0.652563
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x1=1.9099218e-07
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x2=3.4920522e-07
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unitx=n
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divx=5
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subdivx=2
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node="plus%0
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minus%0"
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color="4 5"
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dataset=-1
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linewidth_mult=1.0
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divy=3
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subdivy=1
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rawfile=$netlist_dir/autozero_comp.raw
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sim_type=tran}
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B 2 690 -1020 870 -860 {flags=graph,unlocked
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y1 = 0
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y2 = 0.9
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divy = 5
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x1=0
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x2=148
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divx=5
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subdivx=4
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unitx=1
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linewidth_mult=1.5
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hilight_wave=-1
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dataset=-1
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rawfile=distrib
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sim_type=distrib
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color="4 7 8"
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node="saout
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saout
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0.45"
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sweep="freq0 freq1 freq0"
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mode=HistoH
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xlabmag=2.0}
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B 2 270 -1610 680 -1450 {flags=graph,unlocked
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y1 = 0
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y2 = 0.9
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divy = 5
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x1=1.9099218e-07
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x2=3.4920522e-07
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divx=5
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subdivx=4
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unitx=n
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node="zero0
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zero1
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zero2"
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color="12 4 7"
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linewidth_mult=0.1
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hilight_wave=-1
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rawfile=$netlist_dir/autozero_comp.raw
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sim_type=tran
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rainbow=0
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dataset=235}
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T {CAL} 140 -180 0 1 0.4 0.4 {}
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T {EN} 140 -130 0 1 0.4 0.4 {}
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T {CALIBRATION
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30ns} 400 -260 0 1 0.4 0.4 {}
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T {SENSING
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30ns} 530 -260 0 1 0.4 0.4 {}
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T {OFF} 660 -260 0 1 0.4 0.4 {}
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T {OFF} 210 -260 0 1 0.4 0.4 {}
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T {NGSPICE MISMATCH SIMULATION} 1210 -310 0 0 0.8 0.8 {}
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T {Offset-compensated comparator. Detects +/- 2mv differential signal on PLUS, MINUS.
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Output on SAOUT
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Gaussian Threshold variation (via delvto parameter) is added to all MOS transistors.} 1110 -240 0 0 0.6 0.6 {}
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T {.param ABSVAR=0.05
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delvto='agauss(0,ABSVAR,3)'} 1390 -120 0 0 0.6 0.6 {layer=8}
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T {tcleval(Dataset=[xschem getprop rect 2 0 dataset])} 340 -850 0 0 0.7 0.7 {floater=xxx}
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N 120 -470 120 -450 {lab=TEMPERAT}
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N 360 -530 390 -530 {lab=VSS}
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N 360 -500 360 -480 {lab=VSS}
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N 360 -580 360 -560 {lab=VSSI}
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N 1200 -1160 1230 -1160 {lab=VSS}
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N 1200 -1320 1230 -1320 {lab=VCC}
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N 1170 -1390 1200 -1390 {lab=VCC}
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N 1200 -1390 1200 -1350 {lab=VCC}
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N 1170 -1030 1200 -1030 {lab=VSSI}
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N 1200 -1070 1200 -1030 {lab=VSSI}
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N 1060 -1160 1160 -1160 {lab=ZERO0}
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N 1060 -1250 1060 -1160 {lab=ZERO0}
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N 980 -1250 1060 -1250 {lab=ZERO0}
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N 870 -1250 900 -1250 {lab=#net1}
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N 870 -1430 870 -1250 {lab=#net1}
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N 870 -1430 1300 -1430 {lab=#net1}
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N 1200 -1250 1300 -1250 {lab=#net1}
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N 1690 -1160 1720 -1160 {lab=VSS}
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N 1690 -1320 1720 -1320 {lab=VCC}
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N 1660 -1390 1690 -1390 {lab=VCC}
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N 1690 -1390 1690 -1350 {lab=VCC}
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N 1660 -1030 1690 -1030 {lab=VSSI}
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N 1690 -1070 1690 -1030 {lab=VSSI}
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N 1550 -1160 1650 -1160 {lab=ZERO1}
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N 1550 -1250 1550 -1160 {lab=ZERO1}
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N 1470 -1250 1550 -1250 {lab=ZERO1}
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N 1360 -1250 1390 -1250 {lab=#net2}
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N 1360 -1430 1360 -1250 {lab=#net2}
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N 1360 -1430 1790 -1430 {lab=#net2}
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N 1690 -1250 1790 -1250 {lab=#net2}
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N 1300 -1430 1300 -1250 {lab=#net1}
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N 1200 -1290 1200 -1250 {lab=#net1}
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N 1060 -1320 1060 -1250 {lab=ZERO0}
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N 1690 -1290 1690 -1250 {lab=#net2}
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N 1550 -1320 1550 -1250 {lab=ZERO1}
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N 1790 -1430 1790 -1250 {lab=#net2}
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N 970 -640 1000 -640 {lab=VSS}
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N 1140 -640 1170 -640 {lab=VSS}
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N 1170 -870 1200 -870 {lab=VCC}
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N 940 -870 970 -870 {lab=VCC}
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N 1030 -870 1130 -870 {lab=GN}
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N 1030 -870 1030 -820 {lab=GN}
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N 970 -820 1030 -820 {lab=GN}
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N 970 -740 970 -670 {lab=#net3}
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N 1170 -710 1170 -670 {lab=OUTDIFF}
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N 970 -930 970 -900 {lab=VCC}
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N 1070 -930 1170 -930 {lab=VCC}
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N 1170 -930 1170 -900 {lab=VCC}
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N 1170 -610 1170 -590 {lab=SN}
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N 1070 -590 1170 -590 {lab=SN}
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N 970 -610 970 -590 {lab=SN}
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N 1070 -510 1100 -510 {lab=VSS}
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N 1070 -590 1070 -540 {lab=SN}
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N 1070 -950 1070 -930 {lab=VCC}
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N 1040 -380 1070 -380 {lab=VSSI}
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N 1070 -420 1070 -380 {lab=VSSI}
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N 1550 -510 1580 -510 {lab=VSS}
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N 1550 -870 1580 -870 {lab=VCC}
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N 1520 -940 1550 -940 {lab=VCC}
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N 1550 -940 1550 -900 {lab=VCC}
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N 1520 -380 1550 -380 {lab=VSSI}
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N 1550 -420 1550 -380 {lab=VSSI}
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N 1550 -710 1550 -540 {lab=SAOUTF}
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N 1300 -710 1440 -710 {lab=OUTDIFF}
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N 970 -930 1070 -930 {lab=VCC}
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N 970 -590 1070 -590 {lab=SN}
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N 1200 -1250 1200 -1190 {lab=#net1}
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N 1690 -1250 1690 -1190 {lab=#net2}
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N 1440 -710 1440 -510 {lab=OUTDIFF}
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N 1300 -840 1300 -710 {lab=OUTDIFF}
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N 1790 -840 1790 -710 {lab=SAOUTF}
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N 1790 -710 1930 -710 {lab=SAOUTF}
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N 1170 -710 1300 -710 {lab=OUTDIFF}
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N 1170 -740 1170 -710 {lab=OUTDIFF}
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N 1440 -870 1440 -710 {lab=OUTDIFF}
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N 1550 -1320 1650 -1320 {lab=ZERO1}
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N 1060 -1320 1160 -1320 {lab=ZERO0}
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N 1440 -870 1510 -870 {lab=OUTDIFF}
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N 1440 -510 1510 -510 {lab=OUTDIFF}
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N 2040 -510 2070 -510 {lab=VSS}
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N 2040 -870 2070 -870 {lab=VCC}
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N 2010 -940 2040 -940 {lab=VCC}
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N 2040 -940 2040 -900 {lab=VCC}
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N 2010 -380 2040 -380 {lab=VSSI}
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N 2040 -420 2040 -380 {lab=VSSI}
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N 2040 -710 2040 -540 {lab=SAOUT}
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N 1930 -710 1930 -510 {lab=SAOUTF}
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N 2180 -1160 2210 -1160 {lab=VSS}
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N 2180 -1320 2210 -1320 {lab=VCC}
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N 2150 -1390 2180 -1390 {lab=VCC}
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N 2180 -1390 2180 -1350 {lab=VCC}
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N 2150 -1030 2180 -1030 {lab=VSSI}
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N 2180 -1070 2180 -1030 {lab=VSSI}
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N 2040 -1160 2140 -1160 {lab=ZERO2}
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N 2040 -1250 2040 -1160 {lab=ZERO2}
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N 1960 -1250 2040 -1250 {lab=ZERO2}
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N 1850 -1250 1880 -1250 {lab=#net4}
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N 1850 -1430 1850 -1250 {lab=#net4}
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N 1850 -1430 2370 -1430 {lab=#net4}
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N 2180 -1250 2370 -1250 {lab=#net4}
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N 2180 -1290 2180 -1250 {lab=#net4}
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N 2040 -1320 2040 -1250 {lab=ZERO2}
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N 2370 -1430 2370 -1250 {lab=#net4}
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N 2180 -1250 2180 -1190 {lab=#net4}
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N 2370 -840 2370 -710 {lab=SAOUT}
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N 2040 -1320 2140 -1320 {lab=ZERO2}
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N 1930 -870 2000 -870 {lab=SAOUTF}
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N 1930 -510 2000 -510 {lab=SAOUTF}
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N 1550 -710 1790 -710 {lab=SAOUTF}
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N 2260 -710 2370 -710 {lab=SAOUT}
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N 1930 -870 1930 -710 {lab=SAOUTF}
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N 2040 -840 2040 -710 {lab=SAOUT}
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N 1550 -840 1550 -710 {lab=SAOUTF}
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N 2260 -810 2290 -810 {lab=VCC}
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N 2230 -880 2260 -880 {lab=VCC}
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N 2260 -880 2260 -840 {lab=VCC}
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N 2260 -780 2260 -710 {lab=SAOUT}
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N 720 -590 750 -590 {lab=VCC}
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N 550 -650 550 -620 {lab=SP}
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N 660 -650 750 -650 {lab=SP}
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N 750 -650 750 -620 {lab=SP}
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N 550 -650 660 -650 {lab=SP}
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N 550 -590 580 -590 {lab=VCC}
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N 520 -410 550 -410 {lab=VSS}
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N 750 -410 780 -410 {lab=VSS}
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N 590 -410 710 -410 {lab=GP}
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N 590 -460 590 -410 {lab=GP}
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N 550 -460 590 -460 {lab=GP}
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N 550 -490 550 -460 {lab=GP}
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N 750 -470 750 -440 {lab=OUTDIFF}
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N 750 -380 750 -360 {lab=VSSI}
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N 650 -360 750 -360 {lab=VSSI}
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N 550 -380 550 -360 {lab=VSSI}
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N 620 -320 650 -320 {lab=VSSI}
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N 650 -360 650 -320 {lab=VSSI}
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N 660 -780 690 -780 {lab=VCC}
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N 660 -680 660 -650 {lab=SP}
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N 660 -830 660 -810 {lab=VCC}
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N 750 -470 810 -470 {lab=OUTDIFF}
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N 660 -750 660 -740 {lab=#net5}
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N 550 -460 550 -440 {
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lab=GP}
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N 490 -590 510 -590 {
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lab=MINUS}
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N 790 -590 810 -590 {
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lab=PLUS}
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N 910 -640 930 -640 {
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lab=MINUS}
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N 1210 -640 1230 -640 {
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lab=PLUS}
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N 1300 -1250 1300 -900 {lab=#net1}
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N 1790 -1250 1790 -900 {lab=#net2}
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N 2370 -1250 2370 -900 {lab=#net4}
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N 570 -780 620 -780 {
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lab=GP}
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N 990 -510 1030 -510 {
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lab=GN}
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N 2040 -710 2260 -710 {lab=SAOUT}
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N 550 -360 650 -360 {lab=VSSI}
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N 750 -490 750 -470 {lab=OUTDIFF}
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N 970 -820 970 -800 {lab=GN}
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N 1170 -840 1170 -800 {lab=#net6}
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N 550 -560 550 -550 {lab=#net7}
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N 750 -560 750 -550 {lab=#net8}
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N 1010 -870 1030 -870 {
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lab=GN}
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N 970 -840 970 -820 {
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lab=GN}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {ipin.sym} 110 -850 0 0 { name=p92 lab=CAL }
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C {ipin.sym} 110 -910 0 0 { name=p93 lab=PLUS }
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C {ipin.sym} 110 -950 0 0 { name=p94 lab=MINUS }
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C {ipin.sym} 110 -990 0 0 { name=p95 lab=EN }
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C {ipin.sym} 110 -780 0 0 { name=p96 lab=VSS }
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C {ipin.sym} 110 -810 0 0 { name=p97 lab=VCC }
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C {vsource_arith.sym} 120 -420 0 0 {name=E5 VOL=temper MAX=200 MIN=-200}
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C {lab_pin.sym} 120 -470 0 1 {name=p113 lab=TEMPERAT}
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C {lab_pin.sym} 120 -390 0 0 {name=p114 lab=VSS}
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C {opin.sym} 180 -880 0 0 { name=p116 lab=SAOUT }
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C {lab_pin.sym} 200 -570 0 1 {name=p126 lab=CALB}
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C {lab_pin.sym} 120 -570 0 0 {name=l50 lab=CAL}
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C {code.sym} 840 -190 0 0 {name=STIMULI
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only_toplevel=true
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xxplace=end
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value="* .option SCALE=1e-6
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.option method=gear
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.param VCC=0.9
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.param VDL='VCC/2+0.2'
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.param ABSVAR=0.05
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.temp 25
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.param RNDVAL = 'agauss(0, 10, 1)'
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** to generate following file:
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** copy .../share/doc/xschem/ngspice/stimuli.autozero_comp to simulation directory
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** then do 'Simulation->Utile Stimuli Editor (GUI)' and press 'Translate'
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.include \\"stimuli_autozero_comp.cir\\"
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** download models from here:
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** http://ptm.asu.edu/modelcard/2006/130nm_bulk.pm
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** and save to 'models_autozero_comp.txt' in simulation directory
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.include \\"models_autozero_comp.txt\\"
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* .tran 0.1n 900n uic
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.control
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* setseed 17
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* reset
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* echo Seed=$rndseed
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let run=1
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dowhile run <= 300
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if run > 1
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set appendwrite
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reset
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end
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* save saout cal i(vvcc) en plus minus saoutf outdiff
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save all
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tran 0.5n 900n uic
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write autozero_comp.raw
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let run = run + 1
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end
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quit 0
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.endc
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"}
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C {inv-2.sym} 160 -570 0 0 {name=x14 m=1
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+ wn=0.6u ln=0.2u
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+ wp=1u lp=0.2u
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+ VCCPIN=VCC VCCBPIN=VCC VSSPIN=VSS VSSBPIN=VSS}
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C {inv-2.sym} 160 -700 0 0 {name=x5 m=1
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+ wn=0.6u ln=0.2u
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+ wp=1u lp=0.2u
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+ VCCPIN=VCC VCCBPIN=VCC VSSPIN=VSS VSSBPIN=VSS}
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C {lab_pin.sym} 120 -700 0 0 {name=p15 lab=CALB}
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C {lab_pin.sym} 200 -700 0 1 {name=l4 lab=CALBB}
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C {lab_pin.sym} 390 -530 0 1 {name=p283 lab=VSS}
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C {lab_pin.sym} 320 -530 0 0 {name=l56 lab=EN}
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C {lab_pin.sym} 360 -480 0 0 {name=p284 lab=VSS}
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C {lab_pin.sym} 360 -580 0 0 {name=p199 lab=VSSI}
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C {nmos4-v.sym} 340 -530 0 0 {name=M67 verilog_gate=nmos del=50,50,50 model=nmos w=5u l=0.13u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {parax_cap.sym} 360 -470 0 0 {name=c38 value=2p}
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C {passgate.sym} 940 -1250 0 1 {name=x1 m=1
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+ wn=0.4u ln=0.13u
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+ wp=0.4u lp=0.13u
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+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 940 -1280 0 1 {name=l19 sig_type=std_logic lab=CALB}
|
|
C {lab_pin.sym} 940 -1220 0 1 {name=l44 sig_type=std_logic lab=CALBB}
|
|
C {nmos4-v.sym} 1180 -1160 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1230 -1160 0 1 {name=p179 lab=VSS}
|
|
C {pmos4-v.sym} 1180 -1320 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1230 -1320 0 1 {name=p180 lab=VCC}
|
|
C {lab_pin.sym} 1170 -1390 0 0 {name=p181 lab=VCC}
|
|
C {lab_pin.sym} 1170 -1030 0 0 {name=p182 lab=VSSI}
|
|
C {passgate.sym} 1430 -1250 0 1 {name=x2 m=1
|
|
+ wn=0.4u ln=0.13u
|
|
+ wp=0.4u lp=0.13u
|
|
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1430 -1280 0 1 {name=l45 sig_type=std_logic lab=CALB}
|
|
C {lab_pin.sym} 1430 -1220 0 1 {name=l46 sig_type=std_logic lab=CALBB}
|
|
C {nmos4-v.sym} 1670 -1160 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1720 -1160 0 1 {name=p183 lab=VSS}
|
|
C {pmos4-v.sym} 1670 -1320 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1720 -1320 0 1 {name=p184 lab=VCC}
|
|
C {lab_pin.sym} 1660 -1390 0 0 {name=p185 lab=VCC}
|
|
C {lab_pin.sym} 1660 -1030 0 0 {name=p186 lab=VSSI}
|
|
C {lab_pin.sym} 1550 -1310 0 0 {name=l47 lab=ZERO1}
|
|
C {lab_pin.sym} 1060 -1310 0 0 {name=l48 lab=ZERO0}
|
|
C {nmos4-v.sym} 950 -640 0 0 {name=M20 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {nmos4-v.sym} 1190 -640 0 1 {name=M8 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1000 -640 0 1 {name=p187 lab=VSS}
|
|
C {lab_pin.sym} 1140 -640 0 0 {name=p188 lab=VSS}
|
|
C {pmos4-v.sym} 1150 -870 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1200 -870 0 1 {name=p189 lab=VCC}
|
|
C {pmos4-v.sym} 990 -870 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 940 -870 0 0 {name=p190 lab=VCC}
|
|
C {nmos4-v.sym} 1050 -510 0 0 {name=M32 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1100 -510 0 1 {name=p191 lab=VSS}
|
|
C {lab_pin.sym} 1070 -950 0 0 {name=p192 lab=VCC}
|
|
C {lab_pin.sym} 1040 -380 0 0 {name=p193 lab=VSSI}
|
|
C {nmos4-v.sym} 1530 -510 0 0 {name=M17 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1580 -510 0 1 {name=p194 lab=VSS}
|
|
C {pmos4-v.sym} 1530 -870 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1580 -870 0 1 {name=p195 lab=VCC}
|
|
C {lab_pin.sym} 1520 -940 0 0 {name=p196 lab=VCC}
|
|
C {lab_pin.sym} 1520 -380 0 0 {name=p197 lab=VSSI}
|
|
C {lab_pin.sym} 1790 -750 0 0 {name=l49 lab=SAOUTF}
|
|
C {parax_cap.sym} 1620 -700 0 0 {name=c3 value=4f}
|
|
C {lab_pin.sym} 1300 -750 0 0 {name=l51 lab=OUTDIFF}
|
|
C {lab_pin.sym} 1070 -570 0 0 {name=l52 lab=SN}
|
|
C {lab_pin.sym} 1030 -820 0 1 {name=l53 lab=GN}
|
|
C {parax_cap.sym} 1060 -860 0 0 {name=c5 value=4f}
|
|
C {parax_cap.sym} 990 -580 0 0 {name=c30 value=2f}
|
|
C {parax_cap.sym} 1260 -700 0 0 {name=c31 value=4f}
|
|
C {lab_pin.sym} 990 -510 0 0 {name=p198 lab=GN}
|
|
C {lab_pin.sym} 1230 -640 0 1 {name=l54 lab=PLUS}
|
|
C {lab_pin.sym} 910 -640 0 0 {name=l55 lab=MINUS}
|
|
C {ammeter.sym} 1070 -450 0 0 {name=vdiffn}
|
|
C {ammeter.sym} 1550 -450 0 0 {name=v3}
|
|
C {ammeter.sym} 1690 -1100 0 0 {name=v4}
|
|
C {ammeter.sym} 1200 -1100 0 0 {name=v6}
|
|
C {nmos4-v.sym} 2020 -510 0 0 {name=M19 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 2070 -510 0 1 {name=p9 lab=VSS}
|
|
C {pmos4-v.sym} 2020 -870 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 2070 -870 0 1 {name=p10 lab=VCC}
|
|
C {lab_pin.sym} 2010 -940 0 0 {name=p11 lab=VCC}
|
|
C {lab_pin.sym} 2010 -380 0 0 {name=p12 lab=VSSI}
|
|
C {parax_cap.sym} 2110 -700 0 0 {name=c1 value=4f}
|
|
C {ammeter.sym} 2040 -450 0 0 {name=v1}
|
|
C {lab_pin.sym} 2370 -710 0 1 {name=l3 lab=SAOUT}
|
|
C {passgate.sym} 1920 -1250 0 1 {name=x3 m=1
|
|
+ wn=0.4u ln=0.13u
|
|
+ wp=0.4u lp=0.13u
|
|
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 1920 -1280 0 1 {name=l5 sig_type=std_logic lab=CALB}
|
|
C {lab_pin.sym} 1920 -1220 0 1 {name=l6 sig_type=std_logic lab=CALBB}
|
|
C {nmos4-v.sym} 2160 -1160 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 2210 -1160 0 1 {name=p13 lab=VSS}
|
|
C {pmos4-v.sym} 2160 -1320 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 2210 -1320 0 1 {name=p14 lab=VCC}
|
|
C {lab_pin.sym} 2150 -1390 0 0 {name=p16 lab=VCC}
|
|
C {lab_pin.sym} 2150 -1030 0 0 {name=p17 lab=VSSI}
|
|
C {lab_pin.sym} 2040 -1310 0 0 {name=l8 lab=ZERO2}
|
|
C {ammeter.sym} 2180 -1100 0 0 {name=v5}
|
|
C {pmos4-v.sym} 2240 -810 0 0 {name=M6 verilog_gate=pmos del=50,50,50 model=pmos w=0.6u l=0.2u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 2290 -810 0 1 {name=p18 lab=VCC}
|
|
C {lab_pin.sym} 2230 -880 0 0 {name=p19 lab=VCC}
|
|
C {lab_pin.sym} 2220 -810 0 0 {name=l2 lab=EN}
|
|
C {pmos4-v.sym} 770 -590 0 1 {name=M18 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 720 -590 0 0 {name=p20 lab=VCC}
|
|
C {pmos4-v.sym} 530 -590 0 0 {name=M25 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 580 -590 0 1 {name=p21 lab=VCC}
|
|
C {lab_pin.sym} 520 -410 0 0 {name=p22 lab=VSS}
|
|
C {lab_pin.sym} 780 -410 0 1 {name=p23 lab=VSS}
|
|
C {lab_pin.sym} 620 -320 0 0 {name=p24 lab=VSSI}
|
|
C {pmos4-v.sym} 640 -780 0 0 {name=M28 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {lab_pin.sym} 690 -780 0 1 {name=p25 lab=VCC}
|
|
C {lab_pin.sym} 660 -830 0 0 {name=p26 lab=VCC}
|
|
C {lab_pin.sym} 570 -780 0 0 {name=l7 lab=GP}
|
|
C {lab_pin.sym} 550 -480 0 1 {name=l9 lab=GP}
|
|
C {lab_pin.sym} 490 -590 0 0 {name=l10 lab=MINUS}
|
|
C {lab_pin.sym} 810 -590 0 1 {name=l11 lab=PLUS}
|
|
C {lab_pin.sym} 810 -470 0 1 {name=l12 lab=OUTDIFF}
|
|
C {nmos4-v.sym} 730 -410 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {nmos4-v.sym} 570 -410 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
|
C {parax_cap.sym} 630 -400 0 0 {name=c2 value=4f}
|
|
C {lab_pin.sym} 660 -670 0 0 {name=l13 lab=SP}
|
|
C {launcher.sym} 930 -260 0 0 {name=h2
|
|
descr="Simulate"
|
|
tclcommand="xschem netlist; xschem simulate"}
|
|
C {parax_cap.sym} 1060 -1150 0 0 {name=c4 value=5f}
|
|
C {parax_cap.sym} 1550 -1150 0 0 {name=c6 value=5f}
|
|
C {parax_cap.sym} 2040 -1150 0 0 {name=c7 value=5f}
|
|
C {launcher.sym} 75 -1075 0 0 {name=h1
|
|
descr="Reload
|
|
Waves"
|
|
tclcommand="
|
|
xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
|
|
|
|
proc get_histo \{varname varlist mean min max step\} \{
|
|
xschem raw switch 0
|
|
proc xround \{a size\} \{ return [expr \{round($a/$size) * $size\}]\}
|
|
#### get rounded data
|
|
catch \{unset freq\}
|
|
foreach v1 $varlist \{
|
|
set v1 [xround [expr \{$v1 - $mean\}] $step]
|
|
if \{![info exists freq($v1)]\} \{ set freq($v1) 1\} else \{incr freq($v1)\}
|
|
\}
|
|
#### create histogram raw data in memory
|
|
xschem raw new distrib distrib $varname $min $max $step
|
|
xschem raw add freq0
|
|
set j 0
|
|
for \{set i $min\} \{$i <= $max\} \{set i [expr \{$i + $step\}] \} \{
|
|
set ii [xround $i $step]
|
|
set v1 0
|
|
if \{[info exists freq($ii)]\} \{ set v1 $freq($ii) \}
|
|
xschem raw set freq0 $j $v1
|
|
incr j
|
|
\}
|
|
\}
|
|
|
|
proc add_histo \{varname varlist mean min max step\} \{
|
|
xschem raw switch 1
|
|
proc xround \{a size\} \{ return [expr \{round($a/$size) * $size\}]\}
|
|
#### get rounded data
|
|
catch \{unset freq\}
|
|
foreach v1 $varlist \{
|
|
set v1 [xround [expr \{$v1 - $mean\}] $step]
|
|
if \{![info exists freq($v1)]\} \{ set freq($v1) 1\} else \{incr freq($v1)\}
|
|
\}
|
|
#### create histogram raw data in memory
|
|
xschem raw add freq1
|
|
set j 0
|
|
for \{set i $min\} \{$i <= $max\} \{set i [expr \{$i + $step\}] \} \{
|
|
set ii [xround $i $step]
|
|
set v1 0
|
|
if \{[info exists freq($ii)]\} \{ set v1 $freq($ii) \}
|
|
xschem raw set freq1 $j $v1
|
|
incr j
|
|
\}
|
|
\}
|
|
|
|
|
|
proc get_values \{\} \{
|
|
set l0 \{\}
|
|
set dset [xschem raw datasets]
|
|
set p [xschem raw pos_at time 259n]
|
|
for \{set i 0\} \{ $i < $dset\} \{ incr i\} \{
|
|
set v [xschem raw value saout $p $i]
|
|
lappend l0 $v
|
|
\}
|
|
set l1 \{\}
|
|
set p [xschem raw pos_at time 339n]
|
|
for \{set i 0\} \{ $i < $dset\} \{ incr i\} \{
|
|
set v [xschem raw value saout $p $i]
|
|
lappend l1 $v
|
|
\}
|
|
get_histo saout $l0 0 0 0.9 0.01
|
|
add_histo saout $l1 0 0 0.9 0.01
|
|
xschem raw switch 0
|
|
\}
|
|
|
|
|
|
get_values
|
|
xschem redraw
|
|
|
|
|
|
"
|
|
}
|
|
C {ammeter.sym} 660 -710 0 0 {name=vdiffp}
|
|
C {ammeter.sym} 1300 -870 0 0 {name=vcalib0}
|
|
C {ammeter.sym} 1790 -870 0 0 {name=vcalib1}
|
|
C {ammeter.sym} 2370 -870 0 0 {name=vcalib2}
|
|
C {ammeter.sym} 970 -770 0 0 {name=vnleft}
|
|
C {ammeter.sym} 1170 -770 0 1 {name=vnright}
|
|
C {ammeter.sym} 550 -520 0 0 {name=vpleft}
|
|
C {ammeter.sym} 750 -520 0 0 {name=vpright}
|