52 lines
1.7 KiB
Plaintext
52 lines
1.7 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1"
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}
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V {}
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S {}
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E {}
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L 4 -60 -40 60 -40 {}
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L 4 -60 40 60 40 {}
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L 4 -60 -40 -60 40 {}
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L 4 60 -40 60 40 {}
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L 4 60 -30 80 -30 {}
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L 4 -80 -30 -60 -30 {}
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L 4 -80 -10 -60 -10 {}
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L 4 -80 10 -60 10 {}
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L 4 -80 30 -60 30 {}
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B 5 77.5 -32.5 82.5 -27.5 {name=CODE[5:0] dir=out }
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B 5 -82.5 -32.5 -77.5 -27.5 {name=SIG_IN dir=in }
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B 5 -82.5 -12.5 -77.5 -7.5 {name=VREF dir=in }
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B 5 -82.5 7.5 -77.5 12.5 {name=CK dir=in }
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B 5 -82.5 27.5 -77.5 32.5 {name=RST dir=in }
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T {@symname} -60.25 -53.5 0 0 0.2 0.2 {}
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T {@name} 65 -52 0 0 0.2 0.2 {}
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T {CODE[5:0]} 55 -34 0 1 0.2 0.2 {}
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T {SIG_IN} -55 -34 0 0 0.2 0.2 {}
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T {VREF} -55 -14 0 0 0.2 0.2 {}
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T {CK} -55 6 0 0 0.2 0.2 {}
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T {RST} -55 26 0 0 0.2 0.2 {}
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T {@symname} -10.25 1.5 0 0 0.2 0.2 {}
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