41 lines
1.4 KiB
XML
41 lines
1.4 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 100 -310 120 -310 {
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lab=PLUS}
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N 100 -260 120 -260 {
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lab=MINUS}
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N 230 -290 230 -260 {
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lab=OUT}
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C {opin.sym} 230 -290 0 0 {name=p20 lab=OUT}
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C {ipin.sym} 100 -260 0 0 {name=p1 lab=MINUS}
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C {ipin.sym} 100 -310 0 0 {name=p161 lab=PLUS}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {parax_cap.sym} 120 -300 0 0 {name=C1 gnd=0 value=50f m=1}
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C {parax_cap.sym} 120 -250 0 0 {name=C2 gnd=0 value=50f m=1}
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C {ammeter.sym} 230 -230 0 0 {name=Vmeas}
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C {lab_pin.sym} 230 -200 0 0 {name=p2 sig_type=std_logic lab=0}
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