74 lines
1.8 KiB
Plaintext
74 lines
1.8 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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K {type=NPN_TRANSISTOR
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template="device=NPN_TRANSISTOR name=Q? "
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tedax_format="footprint @name @footprint
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value @name @value
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device @name @device
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@comptag"
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format="@name @pinlist @value "
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}
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G {}
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V {}
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S {}
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E {}
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T {@name} 90 -50 2 1 0.333333 0.333333 {}
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T {Generic_Transistor} 90 -30 2 1 0.333333 0.333333 {}
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L 4 40 -40 60 -20 {}
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L 4 40 -60 60 -80 {}
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L 4 40 -70 40 -30 {}
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L 4 18.4 -50 40 -50 {}
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L 4 56.4 -27.2 60 -20 {}
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L 4 52.8 -23.6 60 -20 {}
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L 4 52.8 -23.6 56.4 -27.2 {}
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A 4 50 -50.1 31.6 0 360 {}
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L 3 60 -100 60 -80 {}
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B 5 57.5 -102.5 62.5 -97.5 {pinnumber=3
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pinseq=1
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name=3
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dir=inout
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}
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T {@#0:pinnumber} 50 -85 2 1 0.2 0.2 {layer=13}
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L 3 0 -50 18.4 -50 {}
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B 5 -2.5 -52.5 2.5 -47.5 {pinnumber=2
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pinseq=2
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name=2
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dir=inout
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}
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T {@#1:pinnumber} 10 -55 2 1 0.2 0.2 {layer=13}
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L 3 60 -20 60 0 {}
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B 5 57.5 -2.5 62.5 2.5 {pinnumber=1
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pinseq=3
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name=1
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dir=inout
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}
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T {@#2:pinnumber} 50 -5 2 1 0.2 0.2 {layer=13}
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