60 lines
1.4 KiB
Plaintext
60 lines
1.4 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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K {type=CAPACITOR
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template="device=CAPACITOR name=C? description=capacitor numslots=0 symversion=0.1 "
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tedax_format="footprint @name @footprint
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value @name @value
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device @name @device
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@comptag"
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format="@name @pinlist @value "
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}
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G {}
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V {}
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S {}
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E {}
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T {@name} 20 -50 2 1 0.333333 0.333333 {}
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L 4 40 -40 40 0 {}
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L 4 50 -40 50 0 {}
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L 4 50 -20 70 -20 {}
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L 4 20 -20 40 -20 {}
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L 3 0 -20 20 -20 {}
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B 5 -2.5 -22.5 2.5 -17.5 {pinnumber=1
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pinseq=1
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name=1
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dir=inout
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}
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L 3 70 -20 90 -20 {}
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B 5 87.5 -22.5 92.5 -17.5 {pinnumber=2
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pinseq=2
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name=2
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dir=inout
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}
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