202 lines
4.7 KiB
XML
202 lines
4.7 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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K {}
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G {}
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V {}
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S {}
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E {}
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T {Components inside this box are inside the device package} 3020 -5690 2 1 0.333333 0.333333 {}
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T {SPICE model of Agilent MSA-2643} 3670 -4920 0 0 0.666667 0.666667 { vcenter=true}
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T {SDB -- 3.31.2003} 4060 -4840 0 0 0.333333 0.333333 { vcenter=true}
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L 4 3000 -5010 3950 -5010 {}
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L 4 3950 -5720 3950 -5010 {}
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L 4 3000 -5720 3950 -5720 {}
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L 4 3000 -5720 3000 -5010 {}
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C {resistor-1.sym} 3230 -5490 3 0 {name=R1
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value=560
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device=RESISTOR
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}
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C {resistor-1.sym} 3230 -5260 3 0 {name=R2
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value=660
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device=RESISTOR
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}
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C {resistor-1.sym} 3390 -5220 3 0 {name=R3
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value=250
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device=RESISTOR
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}
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C {resistor-1.sym} 3680 -5160 3 0 {name=R4
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value=5
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device=RESISTOR
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}
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C {Q_Model.sym} 3300 -5370 0 0 {name=X1
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model-name=Q1_MSA26F
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file=Q1.cir
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device=NPN_TRANSISTOR_subcircuit
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}
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C {Q_Model.sym} 3590 -5290 0 0 {name=X2
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model-name=Q2_MSA26F
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file=Q2.cir
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device=NPN_TRANSISTOR_subcircuit
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}
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C {gnd-1.sym} 3990 -5080 0 0 {}
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C {capacitor-1.sym} 3770 -5160 3 0 {name=C1
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value=4pF
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device=CAPACITOR
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symversion=0.1
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}
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C {vdc-1.sym} 4050 -5130 0 0 {name=Vpwr
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value=DC\\ 5V
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device=VOLTAGE_SOURCE
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footprint=none
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}
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C {vac-1.sym} 2720 -5230 0 0 {name=Vin
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value=dc\\ 0\\ ac\\ 1
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device=vac
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footprint=none
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}
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C {resistor-1.sym} 2770 -5400 0 0 {name=Rth_in
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value=50
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device=RESISTOR
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}
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C {resistor-1.sym} 4230 -5390 3 0 {name=RL
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value=50
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device=RESISTOR
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}
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C {gnd-1.sym} 2740 -5170 0 0 {}
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C {gnd-1.sym} 4070 -5050 0 0 {}
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C {inductor-1.sym} 4090 -5460 3 0 {name=Lc
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value=22nH
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device=INDUCTOR
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symversion=0.1
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}
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C {gnd-1.sym} 4210 -5330 0 0 {}
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C {resistor-1.sym} 4090 -5300 3 0 {name=Rc
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value=50
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device=RESISTOR
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}
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C {capacitor-1.sym} 4110 -5620 0 0 {name=Cout
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value=47pF
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device=CAPACITOR
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symversion=0.1
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}
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C {capacitor-1.sym} 2900 -5390 0 0 {name=Cin
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value=47pF
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device=CAPACITOR
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symversion=0.1
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}
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C {title-B.sym} 2650 -4820 0 0 {}
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C {spice-include-1.sym} 2740 -5760 0 0 {name=A1
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file=./Simulation.cmd
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device=include
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}
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C {inductor-1.sym} 3090 -5130 0 0 {name=L4
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value=0.386nH
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device=INDUCTOR
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symversion=0.1
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}
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C {inductor-1.sym} 3800 -5130 0 0 {name=L6
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value=0.313nH
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device=INDUCTOR
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symversion=0.1
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}
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C {inductor-1.sym} 3090 -5400 0 0 {name=L1
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value=0.833nH
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device=INDUCTOR
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symversion=0.1
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}
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C {inductor-1.sym} 3760 -5630 0 0 {name=L7
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value=0.407nH
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device=INDUCTOR
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symversion=0.1
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}
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C {gnd-1.sym} 2940 -5080 0 0 {}
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C {capacitor-1.sym} 3060 -5230 3 0 {name=Cpara1
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value=0.158pF
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device=CAPACITOR
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symversion=0.1
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}
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C {capacitor-1.sym} 3930 -5240 3 0 {name=Cpara2
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value=0.155pF
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device=CAPACITOR
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symversion=0.1
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}
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C {resistor-1.sym} 3180 -5080 2 0 {name=Rbogus1
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value=1e-12
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device=RESISTOR
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}
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N 3220 -5490 3220 -5350 {}
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N 3220 -5440 3310 -5440 {}
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N 3380 -5380 3380 -5310 {}
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N 3380 -5360 3600 -5360 {}
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N 3670 -5300 3670 -5250 {}
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N 3220 -5640 3220 -5580 {}
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N 3670 -5640 3670 -5420 {}
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N 3380 -5640 3380 -5500 {}
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N 3670 -5160 3670 -5140 {}
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N 3220 -5260 3220 -5140 {}
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N 3380 -5220 3380 -5140 {}
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N 3750 -5270 3750 -5250 {}
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N 3670 -5270 3750 -5270 {}
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N 3750 -5160 3750 -5140 {}
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N 2750 -5410 2770 -5410 {}
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N 2750 -5410 2750 -5350 {lab=Vsource }
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C {lab_wire.sym} 2750 -5410 0 1 {lab=Vsource }
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N 2750 -5230 2750 -5200 {}
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N 4080 -5130 4080 -5080 {}
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N 4220 -5390 4220 -5360 {}
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N 2860 -5410 2900 -5410 {lab=Vin }
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C {lab_wire.sym} 2860 -5410 0 1 {lab=Vin }
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N 4200 -5640 4250 -5640 {lab=Vout }
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C {lab_wire.sym} 4250 -5640 0 1 {lab=Vout }
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N 4220 -5640 4220 -5480 {}
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N 3220 -5640 3760 -5640 {}
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N 4080 -5640 4080 -5550 {}
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N 4080 -5460 4080 -5390 {}
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N 4080 -5300 4080 -5250 {}
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N 3180 -5410 3220 -5410 {}
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N 2990 -5410 3090 -5410 {}
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N 3850 -5640 4110 -5640 {}
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N 2950 -5140 2950 -5110 {}
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N 2950 -5140 3090 -5140 {}
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N 3210 -5140 3800 -5140 {}
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N 3890 -5140 4000 -5140 {}
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N 4000 -5140 4000 -5110 {}
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N 3910 -5640 3910 -5330 {}
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N 3910 -5240 3910 -5140 {}
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N 3040 -5410 3040 -5320 {}
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N 3040 -5230 3040 -5140 {}
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N 3210 -5140 3210 -5070 {}
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N 3190 -5140 3190 -5090 {}
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N 3070 -5090 3190 -5090 {}
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N 3070 -5090 3070 -5070 {}
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N 3070 -5070 3090 -5070 {}
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N 3180 -5070 3210 -5070 {}
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N 3180 -5140 3190 -5140 {}
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