143 lines
3.9 KiB
XML
143 lines
3.9 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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B 2 20 -380 660 -110 {flags=graph
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y1=0
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y2=3
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ypos1=0.0732701
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ypos2=1.90323
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divy=5
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subdivy=1
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unity=1
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x1=-5.76971e-09
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x2=2.9422e-07
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divx=5
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subdivx=1
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node="in
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in_inv
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in_buf
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in_inv2
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in_buf2"
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color="7 4 8 9 10"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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digital=1}
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T {The two below symbols are
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created by a 'symbolgen' script
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that takes a 'buf' or 'inv'
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argument. Schematic also
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created by a 'schematicgen'
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script.} 30 -830 0 0 0.5 0.5 {}
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T {Click on symbol with Control key
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pressed to see the generator script} 90 -620 0 0 0.3 0.3 {}
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T {The two below symbols have a
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schematic created by a
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'schematicgen' script
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that takes a 'buf' or 'inv'
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argument.} 830 -830 0 0 0.5 0.5 {}
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T {Click on symbol with Control key
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pressed to see the generator script} 900 -620 0 0 0.3 0.3 {}
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N 30 -560 30 -520 {
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lab=IN}
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N 30 -560 110 -560 {
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lab=IN}
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N 30 -520 30 -460 {
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lab=IN}
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N 30 -460 110 -460 {
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lab=IN}
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N 190 -560 310 -560 {
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lab=IN_BUF}
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N 190 -460 310 -460 {
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lab=IN_INV}
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N 1000 -460 1120 -460 {
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lab=IN_INV2}
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N 1000 -560 1120 -560 {
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lab=IN_BUF2}
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N 620 -470 620 -440 {
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lab=VCC}
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N 840 -560 840 -520 {
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lab=IN}
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N 840 -560 920 -560 {
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lab=IN}
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N 840 -520 840 -460 {
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lab=IN}
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N 840 -460 920 -460 {
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lab=IN}
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N 470 -640 520 -640 {
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lab=IN}
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N 600 -640 660 -640 {
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lab=IN_BUF3}
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C {symbolgen.tcl(inv,@ROUT\\)} 150 -460 0 0 {name=x1
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tclcommand="edit_file [abs_sym_path symbolgen.tcl]"
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ROUT=1200}
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C {lab_pin.sym} 30 -520 0 0 {name=p1 lab=IN}
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C {symbolgen.tcl(buf,@ROUT\\)} 150 -560 0 0 {name=x3
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tclcommand="edit_file [abs_sym_path symbolgen.tcl]"
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ROUT=1200}
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C {lab_pin.sym} 310 -560 0 1 {name=p2 lab=IN_BUF}
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C {lab_pin.sym} 310 -460 0 1 {name=p3 lab=IN_INV}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {code_shown.sym} 730 -370 0 0 {name=CONTROL
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tclcommand="xschem edit_vi_prop"
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xxplace=end
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value=".include models_rom8k.txt
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.param vcc=3
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vvcc vcc 0 dc 3
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Vin in 0 pwl 0 0 100n 0 100.1n 3 200n 3 200.1n 0
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.control
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save all
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tran 1n 300n uic
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write test_symbolgen.raw
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.endc
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"}
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C {parax_cap.sym} 240 -550 0 0 {name=C1 gnd=0 value=100f m=1}
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C {parax_cap.sym} 240 -450 0 0 {name=C2 gnd=0 value=100f m=1}
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C {launcher.sym} 80 -80 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/test_symbolgen.raw tran"
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}
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C {my_inv.sym} 960 -460 0 0 {name=x2 ROUT=1000
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schematic=schematicgen.tcl(inv)
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tclcommand="edit_file [abs_sym_path schematicgen.tcl]"}
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C {lab_pin.sym} 1120 -460 0 1 {name=p5 lab=IN_INV2}
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C {my_inv.sym} 960 -560 0 0 {name=x4 ROUT=1000
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schematic="schematicgen.tcl(buf,4)"
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tclcommand="edit_file [abs_sym_path schematicgen.tcl]"}
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C {lab_pin.sym} 1120 -560 0 1 {name=p7 lab=IN_BUF2}
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C {vdd.sym} 620 -470 0 0 {name=l2 lab=VCC}
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C {lab_pin.sym} 620 -440 0 1 {name=p8 lab=VCC}
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C {lab_pin.sym} 840 -520 0 0 {name=p9 lab=IN}
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C {parax_cap.sym} 1080 -550 0 0 {name=C3 gnd=0 value=100f m=1}
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C {parax_cap.sym} 1080 -450 0 0 {name=C4 gnd=0 value=100f m=1}
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C {noconn.sym} 840 -560 0 0 {name=l3}
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C {symbolgen.tcl()} 560 -640 0 0 {name=x5
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tclcommand="edit_file [abs_sym_path symbolgen.tcl]"
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ROUT=1200}
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C {lab_pin.sym} 470 -640 0 0 {name=p4 lab=IN}
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C {lab_pin.sym} 660 -640 0 1 {name=p6 lab=IN_BUF3}
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