97 lines
2.9 KiB
XML
97 lines
2.9 KiB
XML
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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L 4 290 -510 290 -210 {}
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L 4 290 -560 290 -510 {}
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P 3 5 400 -440 620 -440 620 -350 400 -350 400 -440 {dash=4}
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P 3 5 140 -250 220 -250 220 -170 140 -170 140 -250 {dash=4}
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P 3 5 140 -540 220 -540 220 -460 140 -460 140 -540 {dash=4}
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P 4 7 710 -390 670 -390 670 -400 640 -390 670 -380 670 -390 710 -390 {}
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P 4 7 290 -510 250 -510 250 -520 220 -510 250 -500 250 -510 290 -510 {}
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P 4 7 290 -210 250 -210 250 -220 220 -210 250 -200 250 -210 290 -210 {}
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T {Resistor generator (res.tcl)
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if a value <= 0.1 is given
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it becomes a short} 720 -410 0 0 0.4 0.4 { layer=4}
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T {Tier generator (tier.tcl)
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if 'lab' matches VDD | VCC | VPP shows
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as supply node, else show as ground node} 240 -640 0 0 0.4 0.4 { layer=4}
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N 180 -300 180 -240 {
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lab=VSS}
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N 180 -480 180 -360 {
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lab=VDD}
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N 460 -480 460 -420 {
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lab=VDD}
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N 180 -480 460 -480 {
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lab=VDD}
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N 570 -480 570 -420 {
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lab=VDD}
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N 460 -480 570 -480 {
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lab=VDD}
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N 460 -360 460 -280 {
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lab=#net1}
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N 570 -360 570 -280 {
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lab=VDD}
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C {tier.tcl(@lab\\)} 180 -480 0 0 {name=p1 sig_type=std_logic lab=VDD
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tclcommand="edit_file [abs_sym_path tier.tcl]"}
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C {tier.tcl(@lab\\)} 180 -240 0 0 {name=p2 sig_type=std_logic lab=VSS
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tclcommand="edit_file [abs_sym_path tier.tcl]"
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}
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C {res.sym} 180 -330 0 0 {name=R1
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value=1k
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footprint=1206
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device=resistor
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m=1
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}
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C {lab_show.sym} 180 -380 0 0 {name=l1}
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C {lab_show.sym} 180 -260 0 0 {name=l2}
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C {capa.sym} 460 -250 0 0 {name=C1
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m=1
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value=1p
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footprint=1206
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device="ceramic capacitor"
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}
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C {capa.sym} 570 -250 0 0 {name=C2
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m=1
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value=1p
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footprint=1206
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device="ceramic capacitor"
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}
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C {tier.tcl(@lab\\)} 460 -220 0 0 {name=p3 sig_type=std_logic lab=VSS}
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C {tier.tcl(@lab\\)} 570 -220 0 0 {name=p4 sig_type=std_logic lab=VSS}
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C {res.tcl(@value\\)} 460 -390 0 0 {name=R2 value=100
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tclcommand="edit_file [abs_sym_path res.tcl]"
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}
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C {res.tcl(@value\\)} 570 -390 0 0 {name=R3 value=0.1
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tclcommand="edit_file [abs_sym_path res.tcl]"
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}
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C {lab_show.sym} 460 -290 0 0 {name=l3}
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C {lab_show.sym} 570 -290 0 0 {name=l4}
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C {title.sym} 160 -30 0 0 {name=l5
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author="Stefan Schippers"
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}
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