47 lines
1.7 KiB
XML
47 lines
1.7 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {
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y <= not a after 0.1 ns ;}
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K {}
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V {assign #150 y=~a ;}
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S {}
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E {}
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N 190 -250 190 -210 {lab=y}
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N 190 -230 230 -230 {lab=y}
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N 150 -280 150 -180 {lab=a}
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N 110 -230 150 -230 {lab=a}
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N 190 -280 270 -280 {lab=VCC}
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N 270 -310 270 -280 {lab=VCC}
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N 190 -310 270 -310 {lab=VCC}
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N 190 -180 290 -180 {lab=0}
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N 290 -180 290 -150 {lab=0}
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N 190 -150 290 -150 {lab=0}
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N 190 -350 190 -310 {lab=VCC}
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N 190 -150 190 -130 {lab=0}
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C {opin.sym} 230 -230 0 0 {name=p1 lab=y verilog_type=wire}
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C {ipin.sym} 110 -230 0 0 {name=p2 lab=a}
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C {p.sym} 170 -280 0 0 {name=m2 model=cmosp w=wp l=lp m=1 }
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C {lab_pin.sym} 190 -350 0 0 {name=p149 lab=VCC}
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C {lab_pin.sym} 190 -130 0 0 {name=p3 lab=0}
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C {n.sym} 170 -180 0 0 {name=m1 model=cmosn w=wn l=lln m=1}
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C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"}
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