52 lines
1.8 KiB
Plaintext
52 lines
1.8 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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function0="1 2 ^ ~"
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verilog_format="xnor #(@risedel , @falldel ) @name ( @#0 , @#1 , @#2 );"
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vhdl_format = "@@Z <= @@A xnor @@B after 0.1 ns;"
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format="@name @pinlist @symname"
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template="name=x1 risedel=400 falldel=300"
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verilog_primitive=true
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vhdl_primitive=true
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}
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V {}
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S {}
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E {}
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L 4 45 0 60 0 {}
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L 4 -40 -20 -26.875 -20 {}
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L 4 -40 20 -26.875 20 {}
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L 4 -25 -30 -5 -30 {}
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L 4 -25 30 -5 30 {}
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B 5 57.5 -2.5 62.5 2.5 {name=Z dir=out verilog_type=wire}
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B 5 -42.5 -22.5 -37.5 -17.5 {name=A dir=in
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goto=0 propag=0}
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B 5 -42.5 17.5 -37.5 22.5 {name=B dir=in
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goto=0 propag=0}
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A 4 40 0 5 180 360 {}
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A 4 -9.642857142857142 17.85714285714286 48.0818286351295 21.80140948635181 62.65738573560834 {}
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A 4 -4.6875 -11.25 41.25118369513777 269.5659493678606 74.60789655596687 {}
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A 4 -65 0 50 323.130102354156 73.7397952916881 {}
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A 4 -72.5 0 50 323.130102354156 73.7397952916881 {}
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T {@symname} -12.5 -12.5 0 0 0.2 0.2 {}
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T {@name} -12.5 2.5 0 0 0.2 0.2 {}
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