122 lines
3.4 KiB
XML
122 lines
3.4 KiB
XML
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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L 7 980 -150 1160 -150 {}
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P 4 7 210 -290 210 -370 220 -370 210 -390 200 -370 210 -370 210 -290 {}
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T {Set tcl variable lvs_ignore to:
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- 1 to short elements with lvs_ignore=short attribute set
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to disable elements with lvs_ignore=open attribute set
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- 0 for normal netlisting} 60 -1030 0 0 1 1 {}
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T {tcleval(lvs_ignore=$lvs_ignore)} 980 -190 0 0 0.6 0.6 {name=l1}
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T {This component has attribute
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lvs_ignore=open} 910 -370 0 0 0.4 0.4 {}
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T {This component has attribute
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lvs_ignore=short} 70 -560 0 0 0.4 0.4 {}
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T {This is the lab_show component
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it is used only to display the net
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name it is attached to. This works if
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Options->Show net names on symbol pins
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is enabled.} 220 -350 0 0 0.4 0.4 {}
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T {This component has
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attribute
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lvs_ignore=open} 470 -650 0 0 0.4 0.4 {}
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N 850 -430 1010 -430 {
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lab=#net1}
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N 850 -430 850 -380 {
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lab=#net1}
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N 50 -540 50 -530 {
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lab=VDD}
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N 50 -470 50 -430 {
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lab=#net2}
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N 50 -430 280 -430 {
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lab=#net2}
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N 360 -430 430 -430 {
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lab=STARTUP}
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N 50 -430 50 -380 {
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lab=#net2}
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N 50 -320 50 -290 {
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lab=GND}
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N 850 -580 850 -570 {
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lab=VDD}
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N 850 -510 850 -430 {
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lab=#net1}
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N 1090 -430 1110 -430 {
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lab=#net3}
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N 850 -320 850 -290 {
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lab=GND}
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N 400 -520 490 -520 {
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lab=STARTUP}
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N 400 -520 400 -430 {
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lab=STARTUP}
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N 550 -520 700 -520 {
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lab=STARTUP}
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C {title.sym} 160 -30 0 0 {name=l1
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author="Stefan Schippers"
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}
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C {launcher.sym} 750 -90 0 0 {name=h1
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descr="Toggle lvs_ignore variable and
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rebuild connectivity"
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tclcommand="
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if \{![info exists lvs_ignore]\} \{
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set lvs_ignore 1
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\} else \{
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set lvs_ignore [expr \{!$lvs_ignore\}]
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\}
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xschem rebuild_connectivity
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xschem unhilight_all
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"}
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C {vsource.sym} 850 -350 0 0 {name=V2 value=0
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lvs_ignore=open}
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C {inv_ngspice.sym} 1050 -430 0 0 {name=x5 ROUT=1000}
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C {lab_show.sym} 920 -430 0 1 {name=l10 }
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C {lab_show.sym} 1110 -430 0 1 {name=l3 }
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C {gnd.sym} 850 -290 0 0 {name=l4 lab=GND}
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C {res.sym} 50 -500 0 0 {name=R1
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value=100MEG
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footprint=1206
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device=resistor
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m=1
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lvs_ignore=short}
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C {vdd.sym} 50 -540 0 0 {name=l12 lab=VDD}
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C {capa.sym} 50 -350 0 0 {name=C1
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m=1
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value=1p
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 50 -290 0 0 {name=l13 lab=GND}
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C {lab_show.sym} 170 -430 2 0 {name=l14 }
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C {lab_pin.sym} 430 -430 0 1 {name=p1 sig_type=std_logic lab=STARTUP}
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C {inv_ngspice.sym} 320 -430 0 0 {name=x2 ROUT=1000}
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C {res.sym} 850 -540 0 0 {name=R2
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value=100MEG
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footprint=1206
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device=resistor
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m=1
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}
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C {vdd.sym} 850 -580 0 0 {name=l6 lab=VDD}
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C {short.sym} 520 -520 1 0 {name=x1 value=0.1 lvs_ignore=open}
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C {lab_show.sym} 700 -520 0 1 {name=l2 }
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