45 lines
1.4 KiB
Plaintext
45 lines
1.4 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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format="tcleval(@name @pinlist @symname [ calc_rc @L @W ])"
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template="name=x1 Res=1e4 Cap=1e-6"
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}
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V {}
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S {}
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E {}
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L 4 -130 -20 130 -20 {}
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L 4 -130 20 130 20 {}
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L 4 -130 -20 -130 20 {}
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L 4 130 -20 130 20 {}
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L 4 130 0 150 0 {}
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L 4 -150 0 -130 0 {}
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B 5 147.5 -2.5 152.5 2.5 {name=OUT dir=out name=p2 }
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B 5 -152.5 -2.5 -147.5 2.5 {name=IN dir=in name=p1 }
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T {@symname} 2 -6 0 0 0.3 0.3 {hcenter=true}
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T {@name} 135 -32 0 0 0.2 0.2 {}
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T {OUT} 125 -4 0 1 0.2 0.2 {}
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T {IN} -125 -4 0 0 0.2 0.2 {}
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T {L=@L
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W=@W} -70 -70 0 0 0.4 0.4 {}
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