70 lines
1.8 KiB
XML
70 lines
1.8 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {
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process
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variable del: time := 0.4 ns;
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variable delay: time;
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variable last : time;
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variable lowvalue: real;
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begin
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wait on ING , USC.cap;
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last := now;
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delay := del * USC.cap;
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print("start pump process: " & pump'PATH_NAME & " " & time'image(now) );
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if(now=0 ns) then
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USC <= RREAL_0;
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elsif ING'event and ING='1' then
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USC.conduct<=conduct;
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transition(USC,val,delay);
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elsif ING'event and ING='0' then
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USC.conduct<=conduct;
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transition(USC,0.0,delay);
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elsif USC.cap'event and USC.cap > USC.cap'last_value and ING='1' then
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lowvalue := USC.value * USC.cap'last_value / USC.cap;
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glitch(USC, lowvalue, val, delay);
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end if;
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end process;
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}
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K {}
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V {}
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S {}
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E {}
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C {iopin.sym} 50 -90 0 0 {name=p1 lab=USC sig_type="rreal"}
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C {ipin.sym} -80 -90 0 0 {name=p2 lab=ING}
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C {use.sym} -150 -260 0 0 {library ieee;
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use std.TEXTIO.all;
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use ieee.std_logic_1164.all;
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library work;
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use work.rrreal_pkg.all;
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}
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