38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=notif0
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verilog_format="not ( @str1 , @str0 ) #( @risedel , @falldel ) @name ( @@Z , @@A );"
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template="name=b1 str1=strong1 str0=strong0 risedel=100 falldel=100"}
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V {}
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S {}
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E {}
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L 4 -40 0 -25 0 {}
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L 4 -25 -20 -25 20 {}
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L 4 -25 -20 15 0 {}
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L 4 -25 20 15 0 {}
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L 4 25 0 40 0 {}
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B 5 37.5 -2.5 42.5 2.5 {name=Z verilog_type=wire dir=out}
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B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in}
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A 4 20 0 5 180 360 {}
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T {@symname} 7.5 -22.5 0 0 0.2 0.2 {}
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T {@name} -23.75 -5 0 0 0.2 0.2 {}
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