42 lines
1.4 KiB
Plaintext
42 lines
1.4 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=subcircuit
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format="@name @pinlist @symname"
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template="name=d1 del=200"}
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V {}
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S {}
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E {}
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L 4 -40 0 -30 0 {}
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L 4 -30 -5 -30 5 {}
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L 4 -30 5 30 5 {}
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L 4 30 -5 30 5 {}
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L 4 -30 -5 30 -5 {}
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L 4 30 -0 40 -0 {}
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L 6 -0 -2.5 20 -0 {}
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L 6 -0 -2.5 0 2.5 {}
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L 6 0 2.5 20 -0 {}
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L 6 -25 0 -0 -0 {}
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B 5 -42.5 -2.5 -37.5 2.5 {name=inp dir=in}
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B 5 37.5 -2.5 42.5 2.5 {name=outp dir=out verilog_type=wire}
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T {del=@del} -37.5 6.25 0 0 0.15 0.12 {}
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T {@name} -20 -12.5 0 0 0.12 0.12 {}
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