46 lines
1.3 KiB
Plaintext
46 lines
1.3 KiB
Plaintext
v {xschem version=3.4.5 file_version=1.2
|
|
*
|
|
* This file is part of XSCHEM,
|
|
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
|
|
* simulation.
|
|
* Copyright (C) 1998-2024 Stefan Frederik Schippers
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
|
}
|
|
G {}
|
|
K {type=netlist_commands
|
|
template="name=COMMANDS
|
|
simulator=ngspice
|
|
only_toplevel=false
|
|
value=\\"
|
|
* ngspice commands
|
|
\\""
|
|
|
|
format="tcleval(
|
|
[if \{[catch \{sim_is_@simulator \} retval] \} \{
|
|
return \{\} \} elseif \{$retval\} \{ return \{
|
|
\\\\@value
|
|
\}
|
|
\} else \{ return \{\} \}
|
|
])"}
|
|
V {}
|
|
S {}
|
|
E {}
|
|
L 4 0 -10 70 -10 {}
|
|
L 4 0 -10 0 10 {}
|
|
T {@name} 5 -50 0 0 0.3 0.3 {}
|
|
T {@value} 15 -5 0 0 0.3 0.3 {font=Monospace}
|
|
T {SIM=@simulator} 5 -30 0 0 0.3 0.3 {}
|